Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-06-05
2001-04-17
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S230030
Reexamination Certificate
active
06219286
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor memories and, more particularly, to semiconductor memories which include nonvolatile memory cells and enable to replace defective memory cells with redundant memory cells.
BACKGROUND OF THE INVENTION
In recent years, in flash memories as nonvolatile semiconductor memories, increased storage capacities and subdivided manufacturing processes result in decreases in the yields. In order to suppress these decreases in the yields, semiconductor memories can avoid a defect in memory cells using redundancy by replacing the faulty defective memory cells with spare memory cells are required.
Japanese Published Patent Application No.5-159597 discloses an example of these semiconductor memories.
FIG. 7
is a diagram schematically illustrating a structure of this conventional semiconductor memory.
In
FIG. 7
, a memory cell array
101
includes memory cells (shown as MC in the figure) which are connected to (n+1) (n: positive integer) word lines WL
1
~W
1
n+1 and m (m: positive integer) bit lines BL
1
~BLm, and arranged like a matrix. Selection circuits Sa
1
~San in a redundancy control circuit
103
switch connections between signal lines R
1
~Rn of a row decoder
102
and the corresponding word lines WLn-WLn+1, respectively. Control cells Ca
1
~Can each have a fuse element or nonvolatile memory cell (not shown) containing defect information. output lines of the control cells Ca
1
~Can are connected to the selection circuits and their adjacent control cells, respectively.
The operation of the semiconductor memory having the above-described structure will be described. The row decoder
102
decodes an input row address, and outputs a decoded result to the signal lines R
1
~Rn. The selection circuits Sa
1
~San receive the outputs of the control cells Ca
1
~Can, and perform the switching. In this case, the i-th (1≦i≦n) selection circuit Sai selects the word line WLi when the output of the control cell Cai is for example “L” (Low level), and selects the word line WLi+1 when the output is “H” (High level) . The control cell Cai contains defect information of WLi. The control cell Cai outputs “H” when the defect information indicates the word line WLi has a defect or the output of Cai−1 is “H”, and outputs “L” in other cases.
For example, when there is a defective memory cell MC in the i-th word line WLi, the defect information is recorded in the control cell Cai, and as for k satisfying the relationship 1≦k<i, the selection circuits Sk are controlled so as to select WLk for Rk and as for j satisfying the relationship i≦j≦n, the selection circuits Sj are controlled so as to select WLj+1 for Rj. That is, the redundancy control circuit
103
replaces defective memory cells with redundant memory cells by shifting the connections of the i-th and subsequent selection circuits to the word lines so as to skip the defective word line WLi as shown in FIG.
7
.
The prior art semiconductor memory comprises the control cells each having the fuse element or nonvolatile memory cell containing the defect information, for all row lines. Accordingly, when the number of row lines is increased in the case of the control cells having the fuse elements, the area of the redundancy control circuit is increased and more time is required for disconnecting the fuse elements. In the case of the control cells having the nonvolatile memory cells, the area is increased due to addition of circuits for writing data, the time for recording data is increased, and further examination of memory cells which contain the defect information separately from the memory cell array is required.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory which can reduce the areas of circuits for replacing defective memory cells with redundant memory cells as well as reduce the time for writing the defect information.
Other objects and advantages of the present invention will become apparent from the detailed description and specific embodiments described are provided only for illustration since various additions and modifications within the spirit and scope of the invention will be apparent to those of skill in the art from the detailed description.
A semiconductor memory according to a 1st aspect of the present invention comprises a memory cell array comprising plural internal connection lines including at least one spare internal connection line, which are arranged successively, and plural memory cells, at least one of which memory cells is connected to each of the internal connection lines; plural external connection lines which are arranged successively; plural selection means, each of which is connected to one of the plural external connection lines and selects either an internal connection line of the plural internal connection lines which is in an arrangement order corresponding to an arrangement order of the connected external connection line or one of at least one internal connection line which is arranged subsequently to the internal connection line, thereby to connect the selected line to the external connection line; a register unit holding an encoded address for specifying at least one defective internal connection line among the internal connection lines, as a defect address; a defect address decoder for decoding the defect address output by the register unit and specifying the defective internal connection line; and plural control means which are provided in correspondence with the plural selection means, each control means controlling the selection of the internal connection line by each of the selection means, so as to select one of the plural internal connection lines except the defective internal connection lines for one of the plural external connection lines according to its arrangement order, on the basis of an output of the defect address decoder. Therefore, the register unit can hold the encoded defect addresses whose number is equal to the number of the spare internal connection lines, whereby it is not required to provide the fuse elements or nonvolatile memory cells for specifying defective internal connection lines, for all the internal connection lines. Accordingly, the area of the circuit for replacing defective memory cells with redundant memory cells can be reduced. Besides, since the register unit contains the encoded defect addresses, the semiconductor memory which enables to reduce the time for writing the defect information can be provided.
According to a 2nd aspect of the present invention, in the semiconductor memory of the 1st aspect, the control means are successively connected each other according to the arrangement orders of the corresponding plural external connection lines, each of the control means outputting a signal for controlling the selection of the internal connection line, to a corresponding one of the selection means and a control means just after that control means, as well as generating the signal for controlling the selection of the internal connection line, which is output to the corresponding one of the selection means, on the basis of a signal which is input by the defect address decoder and a signal for controlling the selection of the internal connection line, which is input by a control means connected just before that control means.
According to a 3rd aspect of the present invention, in the semiconductor memory of the 1st aspect, the plural internal connection liens are (n+2) (n is an positive integer) internal connection lines including two spare internal connection lines; the plural external connection lines are “n” external connection lines; the register unit holds up to two defect addresses for specifying up to two defective internal connection lines; the plural control means are at least “n” control means; and the plural selection means are at least “n” selection means, each selecting either an internal connection line of the (n+2) internal connection lines which is in the arrangement order correspondin
Fuchigami Ikuo
Kataoka Tomonori
Kawai Ken
Kimura Tomoo
Nishida Youichi
Matsushita Electric - Industrial Co., Ltd.
Nelms David
Tran M.
Wenderoth , Lind & Ponack, L.L.P.
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