Semiconductor memory having predecoder control of spare column s

Details Semiconductor memory having predecoder control of spare column s Semiconductor memory having predecoder control of spare column s

1998-09-16

1999-09-21

Nelms, David

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, 36523006, G11C 700

Patent

active

059562765

ABSTRACT:
A decoder for use in addressing a spare column select line for use in a semiconductor random access memory includes a plurality of input lines each connected to a Y predecoder line, each input line including a pass gate for passing the bit connected thereto in response to an enable signal and a fuse link serially connected with a pass gate, a plurality of fuse links being connected in parallel to provide one of a first plurality of address inputs, a logic gate for receiving said first plurality of address inputs from said plurality of input lines and generating a spare column select signal, whereby all decoder pass gates are disabled until the spare word line is selected for use, the address for the spare line being defined by ablation of fuse links in unwanted Y predecoder lines.

REFERENCES:
patent: 5455798 (1995-10-01), McClure
patent: 5471426 (1995-11-01), McClure
patent: 5812466 (1998-09-01), Lee et al.

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