Semiconductor memory having polycrystalline silicon load resisto

Details Semiconductor memory having polycrystalline silicon load resisto Semiconductor memory having polycrystalline silicon load resisto

1991-04-15

1994-10-25

Gossage, Glenn

Static information storage and retrieval

Systems using particular element

Flip-flop

365181, 257297, 257369, 257904, G11C 11417, G11C 702, H01L 2711

Patent

active

053595629

ABSTRACT:
A semiconductor memory device is provided which has a plurality of memory cells each including a pair of cross-coupled metal insulated gate field effect transistors having channels of N-conductivity type, and a pair of load resistors of polycrystalline silicon respectively coupled to the pair of cross-coupled transistors. A peripheral circuit is also provided which is constituted by metal insulated gate field effect transistors having channels of the N-conductivity type and metal insulated gate field effect transistors having channels of P-conductivity type. The semiconductor memory device is formed in an N-type semiconductor substrate, and the pair of cross-coupled metal insulated gate field effect transistors of the memory cells are formed in a well region of P-type which forms a PN-junction with the semiconductor substrate to help reduce the susceptibility to soft errors.

REFERENCES:
patent: 3641511 (1972-02-01), Cricchi et al.
patent: 3760380 (1973-09-01), Hoffman et al.
patent: 3919569 (1975-11-01), Gaensslen et al.
patent: 4044342 (1977-08-01), Suzuki et al.
"4K CMOS ROM," Denshi Zairyo, Jan. 1974, pp. 89-94.

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