Semiconductor memory having parallel test mode

Details Semiconductor memory having parallel test mode Semiconductor memory having parallel test mode

2001-02-08

2002-06-04

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S205000, C365S208000, C365S230030

Reexamination Certificate

active

06400623

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductor memory devices, and more particularly to semiconductor memory devices having efficient parallel multi-bit testing.
BACKGROUND OF THE INVENTION
A semiconductor memory device can typically be arranged into a plurality of banks, which may be independently operated. Each bank may be arranged into a plurality of memory cell plates or arrays, which contain memory cells arranged in rows and columns. Memory cells are selected based on row and column address values.
In an independently operable bank, a row of memory cells is selected by a low order address (row address), which is input into a row decoder. From the selected row of memory cells, a specific cell or cells are selected by a high order address (column address), which is input into a column decoder. Thus, a bit from a memory cell or a group of memory cells can be selected in order to be read out of a semiconductor memory device.
In the read operation, data selected by the address value is output from a memory cell array by way of a data line or input/output (I/O) bus. This data can then be received by a data amplifier (DAMP) and output to a read/write bus (RWBS). The data is then output from the semiconductor memory device by way of an output amplifier or buffer.
As an example, in a semiconductor memory arranged into four banks and having 16 data input/output pins, 16 read/write busses (RWBS) and 64 (16×4) data amplifiers (DAMP) will typically exist.
An example of a block diagram showing a semiconductor memory configured with two banks can be seen in FIG.
3
.
The semiconductor memory of
FIG. 3
contains two independently operable banks (
10
and
20
) shown as BANK A and BANK B. Each bank (
10
and
20
) is connected to a data amplifier DAMP
40
by way of an I/O bus (IOAT/N and IOBT/N). Each bank (
10
and
20
) includes its own DAMP
40
. This allows increased operating speed of the semiconductor memory by reducing the length of the I/O bus from the memory cell array to the DAMP. Read/write bus RWBST/N receives the output of the DAMP
40
. Typically, there may be only one read/write bus RWBST/N per data pin on a chip. Thus in the case of 16 external data pins (×16) there may be only 16 read/write busses RWBST/N. Read/write bus RWBST/N and I/O buses (IOAT/N and IOBT/N) contain both a “true” and a “not true” line, which carry data and complementary data.
In a normal read operation only one DAMP
40
is enabled per read/write bus RWBST/N. This is based on a data amplifier enable signal DAE, which will be activated in accordance with the activated bank (
10
or
20
). Thus, it can be seen that BANK A
10
and BANK B
20
can share the same read/write bus RWBST/N on which data may be read out of either bank (
10
or
20
).
However, in order to decrease test time in a production part, parallel test schemes are implemented that allow multiple bits to be read in parallel, compared with each other and the result of the comparison being output on a data pin. This will allow for instance a ×16 device to have 32 bits being tested in one read cycle which will increase the test throughput, thus reducing test time and therefore reducing manufacturing costs.
In the configuration of
FIG. 3
, a parallel test mode can be implemented by activating both banks (
10
and
20
) and allowing both DAMPs
40
to be activated and operate as a wired-OR/NOR with read/write bus RWBST/N being the output. This can be accomplished by precharging the complementary data line of read/write bus RWBST/N to a high logic/voltage level and having each DAMP
40
pull down (apply a low logic/voltage level) either the “T” or “N” depending on whether the data received from the bank (
10
and
20
) was a zero or one logic value. In the parallel test mode, the same data logic value is output from each bank (
10
and
20
) indicating a “pass”=
0
condition in which only one data line from the read/write bus RWBST/N is pulled down. However, if BANK A
10
outputs a different data logic value than BANK B
20
, one DAMP
40
will pull down one of the data lines from the read/write bus RWBST/N and the other DAMP
40
will pull down the other data line from the read/write bus, thus indicating a “fail” condition. The “pass” or “fail” condition can then be detected by detection circuitry (not shown).
Referring to
FIG. 4
, a circuit schematic diagram of the conventional data amplifier DAMP
40
is set forth. The conventional data amplifier DAMP
40
can be used in the semiconductor memory of FIG.
3
.
The conventional data amplifier
40
includes differential amplifiers (D
1
-D
3
), inverters (L
20
and L
21
), 2-input NOR gates (L
22
and L
23
), and pull down n-channel insulated gate field effect transistors (IGFETs) (N
5
and N
6
). The top conventional data amplifier
40
illustrated in
FIG. 4
, corresponds to DAMP
40
connected to BANK A
10
in FIG.
3
.
FIG. 4
also includes the bottom conventional data amplifier
40
drawn as a box with only pull down IGFETs (N
7
and N
8
) illustrated, however, it is understood that the bottom conventional data amplifier
40
includes the same elements as the top conventional data amplifier
40
. The bottom conventional data amplifier
40
corresponds to DAMP
40
connected to BANK B
20
in FIG.
3
.
The top conventional data amplifier
40
receives data I/O line IOAT and complementary data I/O line IOAN from BANK A
10
as inputs. Top conventional data amplifier
40
also receives data amplifier enable signal DAEA as an input and has outputs connected to read/write bus RWBST/N.
The operation of conventional data amplifier
40
will be explained with reference to the conventional data amplifier connected to BANK A
10
. When data amplifier enable signal DAEA is at a low logic level, top conventional data amplifier
40
of
FIG. 4
is disabled. The low logic level of data amplifier enable signal DAEA is applied to differential amplifiers (D
1
-D
3
) thus placing the differential amplifiers (D
1
-D
3
) in a disable state. The low logic level of data amplifier enable signal DAEA propagates through inverter L
20
and 2-input NOR gates (L
22
and L
23
) to force the gates of n-channel IGFETs (N
5
and N
6
) to a logic low level, thus placing n-channel IGFETs (N
5
and N
6
) in a non-conducting state.
When data amplifier enable signal DAEA is at a high logic level differential amplifiers (D
1
to D
3
) are enabled. Differential amplifier D
1
receives data line IOAT at a positive input terminal and complementary data line IOAN at a negative input terminal while differential amplifier D
2
receives data line IOAT at a negative input terminal and complementary data line IOAN at a positive input terminal. The outputs of differential amplifier D
1
and differential amplifier D
2
are then applied to the positive and negative input terminals of differential amplifier D
3
respectively. In this manner, by applying I/O bus IOAT/N to differential amplifiers (D
1
and D
2
) in a complementary fashion, variations in the process or layout of the differential amplifiers (D
1
and D
2
) that may cause an imbalance can be cancelled. The output of differential amplifier D
3
is then applied to the gate of n-channel IGFET N
5
by way of 2-input NOR gate L
22
. The output of differential amplifier D
3
is also applied to the gate of n-channel IGFET N
6
by way of inverter L
21
and 2-input NOR gate L
22
. In this manner, if I/O bus IOAT/N carries logical one data, the gate of n-channel IGFET N
5
will remain low and the gate of n-channel IGFET N
6
will become high, thus discharging read/write bus line RWBSN. However, if I/O bus IOAT/N carries logical zero data, the gate of n-channel IGFET N
6
will remain low and the gate of n-channel IGFET N
5
will become high, thus discharging read/write bus line RWBST.
It is understood that the bottom conventional data amplifier
40
operates in the same manner as the top conventional data amplifier
40
except the bottom conventional data amplifier
40
has inputs corresponding to BANK B
20
instead of BANK A
10
.
The mi

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