Semiconductor memory having mirroring function

Details Semiconductor memory having mirroring function Semiconductor memory having mirroring function

2001-10-17

2003-05-06

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

For complementary information

C365S063000, C365S220000, C365S230030

Reexamination Certificate

active

06560148

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor memory devices and particularly to semiconductor memory devices having a mirroring function of handling a plurality of bits of memory cells as a 1-bit, pseudo memory cell in accessing data.
2. Description of the Background Art
FIG. 11
schematically shows a configuration of a portion related to data of one bit of a conventional semiconductor memory device. In
FIG. 11
, the semiconductor memory device includes: memory sub arrays MSA
0
-MSAn each having a plurality of memory cells arranged in rows and columns; row decoders RD
0
-RDn provided corresponding to memory sub arrays MSA
0
-MSAn, respectively, each for selecting a row of a corresponding memory sub array; a column decoder CD provided commonly to memory sub arrays MSA
0
-MSAn to select a column in memory sub arrays MSA
0
-MSAn; internal IO line pairs IOP
0
-IOPn provided corresponding to memory sub arrays MSA-MSAn, respectively, and each coupled with a column selected by column decoder CD of a corresponding memory sub array; preamplifiers PAM
0
-PAMn provided corresponding to internal line IO line pairs IOP
0
-IOPn, respectively, and selectively activated to amplify data on their corresponding internal IO line pairs IOP
0
-IOPn and transmit the amplified data to an internal data line pair DBP; and a main amplifier MAP for amplifying the data on internal data line pair DBP and externally outputting the amplified data.
Memory array MA shown in
FIG. 11
configures one IO block and externally communicates data of one bit.
Preamplifiers PAM
0
-PAMn are selectively activated according to an address bit specifying a memory sub array. Internal IO line pairs IOP
0
-IOPn and internal data line pair DBP each transfer data of one bit.
FIG. 12
schematically shows a configuration of memory sub arrays MSA
0
-MSAn shown in FIG.
11
. Since these memory sub arrays MSA
0
-MSAn are identical in configuration,
FIG. 12
shows a configuration of one memory sub array MSAi representatively, wherein i=0 to n.
In
FIG. 12
, memory sub array MSAi includes: a plurality of memory cells MCs arranged in rows and columns; a bit line pair BLP (BLP
0
-BLP
3
) arranged corresponding to each column of memory cells MCs; a word line WL (WL
0
-WLm) arranged corresponding to each row of memory cells MCs; a sense refresh amplifiers SA (SA-SA
3
) provided corresponding to bit line pairs BLP and each activated in response to a signal on sense drive lines S
2
P and S
2
N; a sense amplifier driver SAD for driving sense drive lines S
2
P and S
2
N in response to sense amplifier activation signals ZSOP and SON; and a column select gates CG (CG
0
-CG
3
) provided corresponding to bit line pairs BLP (BLP
0
-BLP
3
), and each operative in response to a column select signal CSL (CSL
0
-CSL
3
) to connect a corresponding bit line pair to internal IO line pair IOP.
Although memory sub array MSAi has a plurality of columns of memory cells arranged therein,
FIG. 12
representatively shows memory cells arranged in four columns.
A memory cell MC includes a capacitor MS for storing information, and an access transistor (an N-channel MOS (insulated gate type) transistor) MT operative in response to a signal on a corresponding word line WL to connect capacitor MS to a corresponding bit line.
Bit line pair BLP includes a bit line BL (BL
0
-BL
3
) and a bit line ZBL (ZBL
0
-ZBL
3
). Memory cell MC is arranged corresponding to a crossing of one of bit lines BL and ZBL of a corresponding bit line pair BLP and a corresponding word line WL.
Sense refresh amplifier SA includes a P sense amplifier configured of cross-coupled P-channel MOS transistors, and cross-coupled N-channel MOS transistors. When sense drive line S
2
P attains a power supply voltage level, the P sense amplifier is activated to drive, to the power supply voltage level, a bit line at a higher potential in a corresponding bit line pair. When sense drive line S
2
N is driven low, the N sense amplifier is activated to drive, to a low level of a ground voltage level for example, a bit line at a lower potential in the corresponding bit line pair.
Sense amplifier driver SAD drives sense drive lines S
2
N and S
2
P to a low level and a high level, respectively, in response to a sense start signal SA and a restore signal GZOP to activate sense refresh amplifier SA (SA
0
-SA
3
).
Column select gate CG (CG
0
-CG
3
) includes transfer gates TX connecting bit lines BL and ZBL of a corresponding bit line pair BLP to IO lines IO and ZIO of internal IO line pair IOP in response to a corresponding column select signal. In response to column select signal CSL (one of CSL
0
-CSL
3
), a column is selected in each memory sub array and bit line pair BLP of a corresponding column is connected to a corresponding internal IO line pair IOP. A data read operation for memory sub arrays shown in the
FIG. 12
will now be described with reference to a signal waveform diagram shown in FIG.
13
.
In a standby state, a bit line precharge/equalization circuit (not shown) precharges and equalizes each bit line BL and ZBL to a voltage level of an intermediate voltage, which is equal to Vcc/2. In the following description, bit lines BL and ZBL will be referred to as generically indicating bit lines BL
0
-BL
3
and ZBL
0
-ZBL
3
shown in FIG.
12
. The bit line precharge/equalization circuit is provided for each bit line pair and it is activated when a bit line precharge/equalization instructing signal BLEQ is at a high level.
In the standby state, internal IO lines ZIO and IO are also precharged to the power supply voltage Vcc level.
When an active cycle starts, a row decoder is first activated to drive a word line WL corresponding to an addressed row to a boosted voltage Vpp level of a selected state. When word line WL is driven to the selected state, a memory cell connected to the selected word line WL has its storage data read on a corresponding bit line BL or ZBL.
FIG. 13
represents a signal waveform when high-level data is read on bit line BL.
Then, when a predetermined period of time elapses, sense start signal SON is activated, sense amplifier driver SAD drives sense drive line S
2
N to a low level. Responsively, sense refresh amplifier SA (generically referring to SA
0
-SA
3
unless otherwise mentioned) is activated and bit line ZBL at a low potential level is discharged to a ground voltage level.
Restore signal ZSOP is then driven to attain a low level and sense drive line S
2
P is responsibly driven to attain the power supply voltage Vcc level. Thus, bit line BL is driven to attain the power supply voltage level. Sense refresh amplifier SA has a configuration of a flip-flop configured of cross-coupled P-channel MOS transistors and cross-coupled N-channel MOS transistors and it has a latch function. After this restoring completes, bit lines BL and ZBL is held by self refresh amplifier SA at a high level and a low level depending on the data of the selected memory cell.
In accessing a column, in response to a column address signal, a column select signal CSL for selecting an addressed column is driven into a selected state by column decoder CD. A corresponding column select gate CG is rendered conducts and bit line pair BLP corresponding to this column select gate is connected to internal IO line pair IOP. Internal IO lines IO and ZIO are clamped in reading data to the power supply voltage Vcc level, and internal IO lines IO and ZIO have their respective potentials varying with the data latched by the sense amplifier. In
FIG. 13
bit line ZBL is at a low level, and internal IO line ZIO attains a voltage level lower than that of internal IO line IO.
A signal of a small amplitude on the internal I/O line is amplified by preamplifier PAM to be a signal of a CMOS level and the amplified signal is transmitted through internal data line pair DBP. When a column select operation completes, column select signal CSL is driven low. The signal on internal data line pair DBP is amplified by the main amplifier at a predetermined timing

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