Semiconductor memory having memory cells and device for...

Details Semiconductor memory having memory cells and device for... Semiconductor memory having memory cells and device for...

2003-03-10

2004-07-20

Phan, Trong (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000, C365S226000

Reexamination Certificate

active

06765818

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor memory having a plurality of memory cells and a semiconductor memory write-in control device for controlling data written in the semiconductor memory, and more particularly to a semiconductor memory and a semiconductor memory write-in control device in which a plurality of storage value fixing memory cells functioning as those of a read only memory are arranged.
2. Description of Related Art
FIG. 6
is a view showing the configuration of a conventional memory cell. In
FIG. 6
, BL denotes a bit line. BL(inverted) denotes an inverted bit line set to a level opposite to that of the bit line BL. WL denotes a word line set to a high level or a low level according to an address signal. INV
1
and INV
2
indicate a pair of inverters cross-connected to each other so as to connect an input end of one inverter to an output end of the other inverter. T
1
and T
2
indicate a pair of n-channel metal-oxide-semiconductor (MOS) transistors connected to both the bit line BL and the inverted bit line BL(inverted) respectively. An output end of the inverter INV
1
is connected to the transistor T
1
, and an output end of the inverter INV
2
is connected to the transistor T
2
. The word line WL is connected to gates of the transistors T
1
and T
2
. When the word line WL is set to the high level, the transistors. T
1
and T
2
are turned on. A conventional memory cell (MC)
10
is composed of the transistors T
1
and T
2
and the inverters INV
1
and INV
2
.
FIG. 7
is a view showing the configuration of a conventional random access memory (RAM) representing a conventional semiconductor memory. In
FIG. 7
, S
11
denotes a read/write request signal output from a central processing unit (CPU) not shown. In a data read operation, the read/write request signal S
11
is output as a read-out request signal set to the low level. In a data write operation, the read/write request signal S
11
is output as a write-in request signal set to the high level. S
12
denotes an address signal output from the CPU. DB(O) to DB(
7
) denote data buses respectively.
10
indicates each of the plurality of conventional memory cells (MC) placed in a memory cell array.
11
indicates a read-write control circuit having both a read-out control circuit such as a sense amplifier (SA) and a write-in control circuit (WC). The pair of bit lines BL and BL(inverted) connected to each read-write control circuit
11
are set to levels opposite to each other in the write-in control circuit (WC) according to a value of bit data transmitted through the corresponding data bus DB in response to the write-in request signal S
11
. Bit data corresponding to different levels of the pair of bit lines BL and BL(inverted) connected to each read-write control circuit
11
is amplified in the read-out control circuit (SA) in response to the read-out request signal S
11
and is output through the corresponding data bus DB.
12
indicates an address decoder (DEC) for receiving the address signal S
12
, selecting one word line WL connected to the memory cells
10
placed on a row of the memory cell array according to the address signal S
12
and setting the selected word line WL to the high level. The conventional RAM shown in
FIG. 7
has a plurality of memory cells
10
shown in
FIG. 6
as basic memory cells (or read/write memory cells).
Next, an operation of the conventional RAM will be described below.
In a data write-in operation for one memory cell
10
, a address signal S
12
indicating a write-in address is transmitted from the CPU to the address decoder
12
, one word line WL connected to the memory cell
10
, in which bit data is planned to be written, is set to the high level according to the address signal S
12
. Therefore, as shown in
FIG. 6
, the transistors T
1
and T
2
of the memory cell
10
are turned on, and the memory cell
10
is electrically connected to both the corresponding bit line BL and the corresponding inverted bit line BL(inverted). Also, the write-in control circuit WC of the read-write control unit
11
connected to both the bit line BL and the inverted bit line BL(inverted) is operated in response to a write-in request signal S
11
, bit data transmitted from the outside through the corresponding data bus DB is written in the memory cell
10
through the write-in control circuit WC of the read-write control unit
11
and the bit line BL and the inverted bit line BL(inverted). In detail, the bit line BL is set to a first bit level (high or low level) according to the bit data, the inverted bit line BL(inverted) is set to a second bit level (low or high level) according to the bit data, the input end of the inverter INV
2
is equalized to the first bit level of the bit line BL through the transistor T
1
, the input end of the inverter INV
1
is equalized to the second bit level of the inverted bit line BL(inverted) through the transistor T
2
.
Also, in a data read-out operation for one memory cell
10
, an address signal S
12
indicating a read-out address is transmitted from the CPU to the address decoder
12
, one word line WL connected to the memory cell
10
, from which bit data is planned to be read out, is set to the high level according to the address signal S
12
. Therefore, the transistors T
1
and T
2
of the memory cell
10
are turned on, and the memory cell
10
is electrically connected to both the corresponding bit line BL and the corresponding inverted bit line BL(inverted), the bit line BL is equalized to a level of the output end of the inverter INV
1
, and the inverted bit line BL(inverted) is equalized to a level of the output end of the inverter INV
2
. Also, the read-out control circuit SA of the read-write control unit
11
connected to both the bit line BL and the inverted bit line BL(inverted) is operated in response to a read-out request signal S
11
, the levels of both the bit line BL and the inverted bit line BL(inverted) are amplified in the read-out control circuit SA to produce bit data, and the bit data is output as bit data stored in the memory cell
10
to the outside through the corresponding data bus DB.
FIG. 8A
is a view showing the configuration of a conventional large scale integration circuit (LSI) manufactured before the determination of preset data and/or preset program codes, and
FIG. 8B
is a view showing the configuration of the conventional LSI manufactured after the determination of preset data and/or preset program codes. In FIG.
8
A and
FIG. 8B
,
14
indicates a CPU.
15
indicates a RAM.
13
indicates an LSI having the RAM
15
and the CPU
14
.
16
indicates an external memory placed at the outside of the LSI
13
.
17
indicates a mask type read only memory (ROM). The RAM
15
and the mask type ROM
17
are operated under the control of the CPU
14
. The external memory
16
is connected to the RAM
15
. The RAM
15
has the same configuration as that of the conventional RAM shown in FIG.
7
.
In an LSI having a RAM and a CPU such as a logic circuit, the onboard RAM is used as a memory for storing data and/or program codes required by an onboard CPU. However, because the RAM denotes a volatile memory, when an electric power supplied to the RAM is stopped, data and/or program codes stored in the RAM are undesirably lost. Therefore, it is required to store preset data and/or preset program codes (for example, a boot program or a self-diagnosis program) required by the onboard CPU to a ROM.
Also, in cases where an apparatus using an LSI is developed for the purpose of the mass production of the apparatus, the apparatus is made many times on an experimental basis, and the performance of the apparatus is tested each time the apparatus is made. In this case, the specification of the LSI is revised each time the apparatus is made on an experimental basis, and it is required to change data and/or program codes preset in the LSI in compliance with the revision of the specification of the LSI. Assuming that preset data and/or preset program codes are

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