Semiconductor memory having improved sensing arrangement

Details Semiconductor memory having improved sensing arrangement Semiconductor memory having improved sensing arrangement

1991-06-17

1993-12-28

Pascal, Robert J.

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

365207, G11C 1140, G11C 700

Patent

active

052745988

ABSTRACT:
A semiconductor memory provided with improved sense amplifier-bit line arrangement which is suitable for a high-speed and high-sensitivity read operation. The memory comprises a main bit line pair, a main sense amplifier, a plurality of sub-bit line pairs and a plurality of sub-sense amplifiers in each column. Each of the sub-sense amplifiers includes a pair of output nodes coupled to the main bit line pair and a pair of input nodes coupled to one of the sub-bit line pairs. A pair of switch elements are inserted between the main bit line pair and each one of the sub-bit line pairs for selectively feeding an output of the main sense amplifier back to one of the sub-bit line pair selected.

REFERENCES:
patent: 4085457 (1978-04-01), Itoh
patent: 4748596 (1988-05-01), Ogura et al.
patent: 4777625 (1988-10-01), Sakui et al.
patent: 4819207 (1989-04-01), Sakui et al.

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