Static information storage and retrieval – Read/write circuit – Differential sensing
Patent
1992-11-06
1994-05-24
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Differential sensing
36518901, 365177, G11C 11413
Patent
active
053155564
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to a semiconductor memory and more particularly to an improvement of a sense amplifier in a static RAM comprised of Bi-CMOS circuits within a semiconductor memory.
In a static RAM comprised of Bi-CMOS circuits, where a bipolar transistor and p-channel and n-channel MOS transistors are present in the same chip, steps are taken to minimize an oscillation of a potential level of a common data line, which oscillation is required to enable both the reading and writing operations, so that a shift between H level and L level that takes place in both directions on the common data line can be made faster.
2. Description of the Related Art
A description will now be given of a static RAM comprised of conventional Bi-CMOS circuits, with reference to FIGS. 1 and 2. FIG. 1 is a circuit diagram of a memory cell and a bit selecting means portion in a conventional static RAM. FIG. 2 is a circuit diagram of a conventional sense amplifier and an I/O portion thereof in a conventional static RAM. Referring to FIG. 1, this static RAM comprises a number of memory cells 11, 11' disposed in respective columns 33 and 33' and in respective rows. The memory cells 11 and 11' in the columns 33 and 33' are supplied with respective signal lines Xm and Xm' from respective word lines 20 and 20' in each row. When the signal lines Xm and Xm' are at a logical level "H", either of the memory cells 11 or 11' becomes connected to a pair of bit lines 25a and 25b disposed in each column.
Bit selecting means 32 and 32' are disposed in correspondence with each pair of bit lines 25a and 25b, and comprise a column switch consisting of two pairs of transistors; namely a pair of n-channel MOS transistors 8a, 9a and a pair of p-channel MOS transistors 8b, 9b, and further comprising bit line load transistors 10a and 10b consisting of p-channel MOS transistors. Each of the column switches 8a and 8b begins conducting in response to the logical level "L" of a column address Yn, and connects the corresponding pair of bit lines 25a and 25b to a pair of common data lines 26a and 26b. Also, the bit load transistors 10a and 10b begin conducting so as to connect the pair of bit lines 25a and 25b to a constant-voltage regulated power supply VRS (-0.8 V, for example) 22. After the column switches 8a and 8b begin conducting, the common data lines 26a and 26b connect one of the memory cells 11 or 11' selected in accordance with a column address and a row address to a sense amplifier.
Referring to FIG. 2, a sense amplifier 31 comprises: a differential amplifier constituting an ECL circuit, which amplifier allows the signals on the common data line 26a and 26b to be received at the bases of bipolar transistors 5a and 5b and outputs the amplified results as outputs 16a and 16b of the sense amplifier 31; a pair of write n-channel MOS transistors 4a and 4b constituting a write means for receiving an input of a signal consisting of a write signal and a write data, and connecting either of the common data lines 26a and 26b to a VEE power supply (-4.5 V, for example) 24 on the basis of the write data; data line load transistors 3a and 3b consisting of a pair of p-channel MOS transistors, which transistors conduct when the write transistors 4a and 4b are OFF, thus allowing connection between the VRS power supply 22 and each of the common data lines 26a and 26b, and supplying a read current to a memory cell at the read operation time.
Gates are disposed in the input portion of the sense amplifier 31; namely a pair of NOR gates 2a and 2b which receive an input of a write signal WE' (hereinafter WE' represents a WE having a top bar) at one of the terminals thereof, and a data input gate 1 which, upon receipt of a write data Din, feeds this write data and an inverted signal on the basis of the write data to the other terminal of the above-mentioned NOR gates 2a and 2b, respectively. The outputs from each of the NOR gates 2a and 2b are fed to the inputs of the gates of the write transistors 4a and
REFERENCES:
patent: 4078261 (1978-03-01), Millhollan
patent: 4961170 (1990-10-01), Maki et al.
patent: 5168467 (1992-12-01), Fukushi
Fujitsu Limited
Popek Joseph A.
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