Semiconductor memory having embedding lockable cells

Static information storage and retrieval – Floating gate – Particular connection

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Details

711170, 36518513, 36518529, 36523003, G11C 1604

Patent

active

059205040

ABSTRACT:
A semiconductor memory is disclosed having lockable cells which can be programmed or erased to store the information of an erasure lock or an erasure unlock without disturbing data stored in memory cells. The memory includes a memory cell array formed of a plurality of blocks, the blocks formed of a plurality of memory cells which are coupled to a plurality of memory word lines and bit lines, a lockable cell array formed of a plurality of lockable cells which are coupled to a lockable bit line and a plurality of lockable word lines which are electrically isolated from the memory word lines, and a lockable decoding circuit to generate a plurality of decoding signals to select the lockable word lines independent upon a selection of the memory word lines.

REFERENCES:
patent: 5515319 (1996-05-01), Smayling et al.
patent: 5737258 (1998-04-01), Choi et al.
patent: 5809553 (1998-09-01), Choi et al.

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