Semiconductor memory having dummy regions in memory cell array

Details Semiconductor memory having dummy regions in memory cell array Semiconductor memory having dummy regions in memory cell array

2006-01-17

2006-01-17

Ho, Hoai (Department: 2827)

Static information storage and retrieval

Read/write circuit

Including signal comparison

C365S205000, C365S230030

Reexamination Certificate

active

06987698

ABSTRACT:
A memory cell array is partitioned into a plurality of memory regions each of which includes a plurality of sense amplifiers and each of which is established as a unit of data input/output. Dummy regions each are formed between every two memory regions and include dummy bit lines that are set to a predetermined voltage at least during the operation of the memory cell array. Since the dummy bit lines are wired between the bit lines of the two adjacent memory regions, the voltage change in the bit lines in any of the memory regions can be prevented from affecting the bit lines in the other memory regions. As a result, malfunction of semiconductor memories can be prevented.

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