Semiconductor memory having dummy bit line...

Details Semiconductor memory having dummy bit line... Semiconductor memory having dummy bit line...

2007-10-02

2007-10-02

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S185200, C365S185250

Reexamination Certificate

active

11480911

ABSTRACT:
Reset dummy cells which change the load capacitance of a dummy read line DRD according to stored information are provided. Memory information are set to the reset dummy cells according to environmental factors, such as the temperature condition, voltage condition, etc. The timing of reading data from memory cells is controlled according to a change in voltage of the dummy read line DRD which is caused due to the discharge of the precharged dummy read line DRD.

REFERENCES:
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patent: 6760269 (2004-07-01), Nakase et al.
patent: 6804153 (2004-10-01), Yoshizawa et al.
patent: 6982899 (2006-01-01), Sumitani et al.
patent: 2002/0159309 (2002-10-01), Yamanaka
patent: 2005/0073885 (2005-04-01), Suzuki et al.
patent: 2001-351385 (2001-12-01), None

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