Semiconductor memory having differential bit lines

Details Semiconductor memory having differential bit lines Semiconductor memory having differential bit lines

1999-05-20

2000-11-07

Elms, Richard

Static information storage and retrieval

Read/write circuit

For complementary information

365149, 365207, G11C 700

Patent

active

061445908

ABSTRACT:
In a semiconductor memory, bit lines are disposed in such a way that in each case two inverted and two non-inverted bit lines lie next to one another. Adjacent switching transistors for connecting the bit lines to an inverted or a non-inverted collective line are connected to the corresponding collective line by a common contact. An advantage in terms of area is afforded by the fact that the two switching transistors have a common doping region.

REFERENCES:
patent: 4476547 (1984-10-01), Miyasaka
patent: 4875192 (1989-10-01), Matsumoto
patent: 4979013 (1990-12-01), Furutani et al.
patent: 5280443 (1994-01-01), Hidaka et al.
patent: 5383159 (1995-01-01), Kubota
patent: 5666319 (1997-09-01), Okmura
patent: 5875138 (1999-02-01), Hoenigschmid
patent: 5929494 (1999-07-01), Li

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