Semiconductor memory having decoded sense amplifier drive lines

Details Semiconductor memory having decoded sense amplifier drive lines Semiconductor memory having decoded sense amplifier drive lines

1995-10-26

1997-04-29

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

365190, G11C 700

Patent

active

056255993

ABSTRACT:
In a DRAM or similar memory having sense amplifiers coupled to memory cells, a sense amplifier is switchably connected to a discharge circuit to discharge the terminal of the sense amplifier at high speed. The node of the sense amplifier is also coupled to a discharge circuit which discharges the node at a slower speed. In operation, only the node of a selected sense amplifier is discharged at high speed, while other non-selected sense amplifiers are activated by discharging the sense amplifier node at a lower speed. This mode of operation allows for the high speed activation of the selected sense amplifier with the associated current consumption being limited to that necessary to discharge the individual sense amplifier selected. The two discharge circuits may be two N channel MOS transistors connecting the node of the sense amplifier to two drive lines driven by independent circuits. The higher speed discharge circuit is implemented as an N channel MOS transistor which is switched by a signal from the column select line.

REFERENCES:
patent: 4158241 (1979-06-01), Takemae et al.
patent: 4780850 (1988-10-01), Miyamoto
patent: 5023842 (1991-06-01), Okada
patent: 5367493 (1994-11-01), Yamagata

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