Semiconductor memory having charge trapping memory cells

Details Semiconductor memory having charge trapping memory cells Semiconductor memory having charge trapping memory cells

2006-07-11

2006-07-11

Tran, Mai-Huong (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S437000, C257SE21673, C257SE27081, C438S072000, C438S636000, C438S736000, C438S740000

Reexamination Certificate

active

07075137

ABSTRACT:
In a charge trapping memory architecture for virtual ground with interconnects (6) that are present parallel to the word lines (2) and STI isolations (1) that are present parallel to the bit lines (4), provision is made of STI isolations (7) that are widened for division into slices. Instead of this, the interconnects present below a bit line may be omitted or two mutually adjacent bit lines (41, 42) may be wired up in such a way that the memory transistors present between them operate only in the dummy mode.

REFERENCES:
patent: 5311049 (1994-05-01), Tsuruta
patent: 5583808 (1996-12-01), Brahmbhatt
patent: 5825688 (1998-10-01), Ueki
patent: 6713315 (2004-03-01), Kuo et al.
patent: 102 58 194 (2004-07-01), None

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