Semiconductor memory having burst transfer function and...

Details Semiconductor memory having burst transfer function and... Semiconductor memory having burst transfer function and...

2005-01-25

2005-01-25

Yoha, Connie C. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S233100, C365S230080, C365S230090, C365S189050, C365S189070

Reexamination Certificate

active

06847570

ABSTRACT:
A refresh control circuit generates a refresh request in a predetermined cycle. A first burst control circuit outputs a predetermined number of strobe signals in accordance with an access command. A burst access operation is executed by an access command. A data input/output circuit successively inputs data to be transferred to a memory cell array or successively outputs data supplied from the memory cell array, in synchronization with the strobe signals. An arbiter determines which of a refresh operation or a burst access operation is to be executed first, when the refresh request and the access command conflict with each other. Therefore, the refresh operation and burst access operation can be sequentially executed without being overlapped. As a result, read data can be outputted at a high speed, and write data can be inputted at a high speed. That is, the data transfer rate can be improved.

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European Search Report, Aug. 13, 2004 for EP 02025813.

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