Semiconductor memory having built-in test circuit

Details Semiconductor memory having built-in test circuit Semiconductor memory having built-in test circuit

1991-01-31

1993-11-09

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Testing

365200, 371 211, 371 71, G11C 2900, G06F 1100

Patent

active

052609065

ABSTRACT:
A semiconductor memory comprises memory cell arrays and data amplifiers, four or more respectively, and two common read buses for them. Each data amplifier outputs the first and second data having respective levels complementary to each other. It further comprises the first and second logic circuits. Each logic circuit is composed of a plurality of transistors, each being located adjacent to the respective corresponding data amplifier, to the gate of each the first and second data being applied, and the drain of each being connected to the two read buses. The semiconductor memory further comprises the third logic circuit into which the data from the two read buses are input. The number of data buses needed can be reduced to only three in total for write and read operations independent of the number of memory cell arrays, contributing to minimization of chip area.

REFERENCES:
patent: 4464750 (1984-08-01), Tatematsu
patent: 4685086 (1987-08-01), Tran
patent: 4873669 (1989-10-01), Furutani et al.
patent: 4885748 (1989-12-01), Hoffmann et al.
patent: 4896322 (1990-01-01), Kraus et al.

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