Semiconductor memory having bit lines with isolation circuits co

Details Semiconductor memory having bit lines with isolation circuits co Semiconductor memory having bit lines with isolation circuits co

1988-04-01

1991-06-04

Gossage, Glenn

Static information storage and retrieval

Read/write circuit

Bad bit

365 51, 371 103, G11C 700, G11C 11407

Patent

active

050220063

ABSTRACT:
A semiconductor memory device is described in which wordline redundancy is implemented without impacting the access time. A redundant decoder circuit generates a wordline drive inhibit signal which inhibits the generation of a normal wordline signal. Deselection also deselects the normally accessed reference cells, requiring that the redundant cells provide their own reference signal. This last requirement is accomplished by utilization of twin cells for the redundant memory. Placing the redundant memory cells on the sense node side of the bit line isolators enables the effective doubling of the number of redundant cells available each of a plurality of sub-arrays of normal memory.

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