Semiconductor memory having an error correction function

Details Semiconductor memory having an error correction function Semiconductor memory having an error correction function

2007-05-01

2007-05-01

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000, C365S198000, C365S189080

Reexamination Certificate

active

11155731

ABSTRACT:
Regular data inputted/outputted to/from external terminals is read/written to/from a regular cell array, and parity data is read/written from/to a parity cell array. Since the parity data is generated by a parity generation circuit, it is difficult to write a desired pattern to the parity cell array. The regular data and the parity data are exchanged with each other by a switch circuit, so that the regular data can be written to the parity cell array and the parity data can be written to the regular cell array. This enables the write of desired data to the parity cell array. A test of the parity data can be easily conducted. In particular, a leakage test or the like between memory cells can be easily conducted.

REFERENCES:
patent: 6430073 (2002-08-01), Batson et al.
patent: 7106642 (2006-09-01), Hojo
patent: 2001/0052090 (2001-12-01), Mio
patent: 05-054697 (1993-03-01), None

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