Semiconductor memory having access transistors formed in a...

Details Semiconductor memory having access transistors formed in a... Semiconductor memory having access transistors formed in a...

2002-12-03

2004-05-11

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Fet configuration adapted for use as static memory cell

C257S206000

Reexamination Certificate

active

06734573

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly to an improvement in soft error immunity.
2. Description of the Background Art
FIG. 16
is a circuit diagram showing a conventional semiconductor memory
1
R.
FIG. 16
illustrates a memory cell
10
R and accompanying two (i.e., a pair of) bit lines BL
1
R, BL
2
R and a word line WLR. The memory cell
10
R is a memory cell of a so-called single port SRAM (Static Random Access Memory).
As shown in
FIG. 16
, the memory cell
10
R is formed by two driver transistors
11
DNR,
12
DNR, two load transistors
11
LPR,
12
LPR, and two access transistors
11
ANR,
12
ANR. Access transistors may be called transfer transistors or transfer gates. In the conventional semiconductor memory
1
R, the driver transistors
11
DNR,
12
DNR and access transistors
11
ANR,
12
ANR are each composed of an N-type (N-channel type) MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), while the load transistors
11
LPR,
12
LPR are each composed of a P-type (P-channel type) MOSFET.
The driver transistor
11
DNR and load transistor
11
LPR are connected in series to form a CMOS type inverter
11
R. Likewise, the driver transistor
12
DNR and load transistor
12
LPR are connected in series to form a CMOS type inverter
12
R. The two inverters
11
R and
12
R are connected in parallel between a power supply potential VDD and a ground potential GND.
A connection point
11
b
R between the driver transistor
11
DNR and load transistor
11
LPR, i.e., an output terminal
11
b
R of the inverter
11
R is connected to the bit line BL
1
R through the access transistor
11
ANR. Further, the output terminal
11
b
R of the inverter
11
R is connected to an input terminal
12
a
R of the inverter
12
R, that is, connected in common to the gates of the two transistors
12
DNR and
12
LPR. Likewise, a connection point
12
b
R between the driver transistor
12
DNR and load transistor
12
LPR, i.e., an output terminal
12
b
R of the inverter
12
R is connected to the bit line BL
2
R through the access transistor
12
ANR. Further, the output terminal
12
b
R of the inverter
12
R is connected to an input terminal
11
a
R of the inverter
11
R, that is, connected in common to the gates of the two transistors
11
DNR and
11
LPR. The gates of the access transistors
11
ANR and
12
ANR are both connected to the word line WLR.
Since the output terminals
11
b
R and
12
b
R of the inverters
11
R and
12
R correspond to so-called storage nodes of the memory cell
10
R, these storage nodes are designated by the same reference characters
11
b
R and
12
b
R as the output terminals
11
b
R and
12
b
R for convenience's sake.
Next, a specific structure of the conventional semiconductor memory
1
R will be described referring to layout views (plan views) shown in
FIGS. 17
to
21
. For ease of description, part of components of the conventional semiconductor memory
1
R shown in
FIG. 17
is extracted and shown in
FIGS. 18
to
21
. Further, for ease of description, first and second directions D
1
and D
2
are indicated as being parallel to a main surface
5
SR of a semiconductor substrate
5
R and perpendicular to each other.
As shown in
FIGS. 17
to
21
, three wells WP
1
R, WNR and WP
2
R are formed in the main surface
5
SR of the semiconductor substrate
5
R and are aligned in this order in the first direction D
1
.
As shown in
FIG. 18
, an N-type driver transistor
11
DNR and an N-type access transistor
11
ANR are formed in the well WP
1
R of P-type. P-type load transistors
11
LPR,
12
LPR are formed in the well WNR of N-type. Further, an N-type driver transistor
12
DNR and an N-type access transistor
12
ANR are formed in the well WP
2
R of P-type.
Specifically, N
+
-type impurity regions FN
32
R, FN
10
R and FN
20
R constituting source/drain regions of N-type MOSFETs are formed in the main surface
5
SR in the P-well WP
1
R. The impurity regions FN
32
R and FN
10
R are aligned in the second direction D
2
with a channel region of the driver transistor
11
DNR interposed therebetween, and the impurity regions FN
10
R and FN
20
R are aligned in the second direction D
2
with a channel region of the access transistor
11
ANR interposed therebetween. Here, the two transistors
11
DNR and
11
ANR share the impurity region FN
10
R.
Likewise, N
+
-type impurity regions FN
33
R, FN
11
R and FN
21
R are formed in the main surface
5
SR in the P-well WP
2
R. The impurity regions FN
33
R and FN
11
R are aligned in the second direction D
2
with a channel region of the driver transistor
12
DNR interposed therebetween, and the impurity regions FN
11
R and FN
21
R are aligned in the second direction D
2
with a channel region of the access transistor
12
ANR interposed therebetween. Here, the two transistors
12
DNR and
12
ANR share the impurity region FN
11
R.
On the other hand, P
+
-type impurity regions FP
12
R, FP
10
R, FP
13
R and FP
11
R constituting source/drain regions of P-type MOSFETs are formed in the main surface
5
SR in the P-well WP
2
R. The impurity regions FP
12
R and FP
10
R are aligned in the second direction D
2
with a channel region of the load transistor
11
LPR interposed therebetween, and the impurity regions FP
13
R and FP
11
R are aligned in the second direction D
2
with a channel region of the load transistor
12
LPR interposed therebetween.
The channel regions of the transistors
11
DNR,
11
LPR and
12
ANR are aligned in the first direction D
1
, and the channel regions of the transistors
12
DNR,
12
LPR and
11
ANR are aligned in the first direction D
1
.
A gate interconnect line PL
11
R is provided to be opposite to the channel regions of the transistors
11
DNR and
11
LPR with a gate oxide film (not shown) interposed therebetween. Further, the gate interconnect line PL
11
R is in contact with the impurity region FP
11
R. Likewise, a gate interconnect line PL
12
R is provided to be opposite to the channel regions of the transistors
12
DNR and
12
LPR with a gate oxide film (not shown) interposed therebetween. Further, the gate interconnect line PL
12
R is in contact with the impurity region FP
10
R. Likewise, gate interconnect lines PL
11
AR and PL
12
AR are provided to be opposite to the channel regions of the access transistors
11
ANR and
12
ANR, respectively, with a gate oxide film (not shown) interposed therebetween. The gate interconnect lines PL
11
R, PL
12
R, PL
11
AR and PL
12
AR are made of, e.g., low resistance polysilicon.
An interlayer insulation film (not shown) is provided to cover the impurity region FN
32
R and the like and the gate interconnect lines PL
11
R, PL
12
R, PL
11
AR and PL
12
AR. Contact holes CR reaching the impurity regions FN
32
R, FN
10
R, FN
20
R, FN
33
R, FN
11
R, FN
21
R, FP
12
R and FP
13
R, respectively, are formed in the interlayer insulation film. Further, a contact hole (also referred to as shared contact hole) SCR, to the inside of which the gate interconnect line PL
11
R and impurity region FP
11
R are both exposed, and a shared contact hole SCR, to the inside of which the gate interconnect line PL
12
R and impurity region FP
10
R are both exposed, are formed in the interlayer insulation film. Moreover, contact holes (also referred to as gate contact holes) GCR reaching the gate interconnect lines PL
11
AR and PL
12
AR, respectively, are further formed in the interlayer insulation film.
Next, as will be appreciated from
FIGS. 18 and 19
, first layer interconnect lines
1
WR,
1
GR,
1
DR,
1
B
1
R,
1
B
2
R,
1
L
1
R and
1
L
2
R made of, e.g., aluminum are provided on the interlayer insulation film.
The two interconnect lines
1
WR are in contact with the gate interconnect lines PL
11
AR and PL
12
AR, respectively, through the gate contact holes GCR, while the two interconnect lines
1
GR are in contact with the impurity regions FN
32
R and FN
33
R, respectively, through the contact holes CR. Further, the two interconnect lines
1
DR are in contact with the impurity regions FP
12
R and FP
13

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