Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Reexamination Certificate
2002-02-07
2003-02-04
Lam, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
C365S189011, C365S203000
Reexamination Certificate
active
06515927
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor memory and more particularly to a semiconductor memory having a wide bus-bandwidth for input/output data.
2. Description of the Related Art
In general, a semiconductor memory includes memory cells arranged at the respective intersections of word lines and bit lines wired vertically and horizontally. The bit lines are connected to sense amplifiers that amplify data to be inputted to and data outputted from the memory cells.
In a read operation of this kind of semiconductor memory, a word line is selected in accordance with an address signal (a row address signal) supplied from the exterior of the memory, and the data held in the memory cells are transferred to the bit lines. The sense amplifiers amplify the data transferred onto the bit lines. Besides, in accordance with address signals (column address signals), part of the amplified data are selected and outputted to the exterior of the memory as a read data. The data amplified by the sense amplifiers (including the remaining data that are not read out to the exterior) are rewritten into the memory cells, and the read operation is completed.
In a write operation, first of all, similarly to the read operation, a word line is selected in accordance with a row address signal, and data are outputted from the memory cells. The data read out onto the bit lines are amplified by the sense amplifiers. After the sense amplifiers start their amplifying operations, write data from the exterior are transferred to the bit lines selected in accordance with column address signals. At this moment, on the selected bit lines, if the data read from the memory cells are different from the write data, the levels of the bit lines are inverted. Then, the write data are written into the memory cells. On the unselected bit lines, the data amplified by the sense amplifiers are rewritten into the memory cells.
Conventionally, as described above, only the part of the data amplified by the sense amplifiers are outputted to the exterior as the read data or written into the memory cells as the write data. In other word, the sense amplifiers directly contributing to the read and write operations are only part of the activated sense amplifiers.
For example, in a case when 512 memory cells are connected to each word line, during a read operation (or a write operation), 512 sense amplifiers are simultaneously activated. In such a case, if the data input/output terminals are of 8 bits, the number of sense amplifiers directly contributing to a read operation is only eight, which is only {fraction (1/64)} of the number of activated sense amplifiers. The remaining {fraction (63/64)} thereof, that is, 504 sense amplifiers operate just for rewriting the data into the memory cells. That is, the sense amplifiers that are not necessary to particular data input/output operations are activated unnecessarily.
Since each of the bit lines is connected to a plurality of memory cells, its wiring length is long and its load capacitance is large. Since the sense amplifiers must charge and discharge the bit lines having a large load capacitance, their power consumption is larger as compared with the power consumption of other logical circuits in the memory. Thus, charging and discharging the bit lines unnecessarily prevents the reduction of power consumption. Besides, since the sense amplifiers directly contributing to the data input/output operations are only part of the activated sense amplifiers as described above, there is a problem that the power consumption per unit amount of inputted/outputted data is large.
Conventionally, in order to raise the data transfer rate, some approaches to broaden the bus bandwidth of the inputted/outputted data are adopted. In these approaches, however, it is not attempted to modify the ratio of the number of sense amplifiers contributing to the read and write operations to the number of sense amplifiers operating only to rewrite the data. Accordingly, when the bus bandwidth of the input/output data is doubled, the number of simultaneously activated sense amplifiers is also doubled.
Raising the data transfer rate may be also realized by raising the operational frequency of the semiconductor memory. However, if the operational frequency f is raised, it will increase the charge and discharge currents of the transistors, causing the circuit power consumption P to become large, as can be seen from the following equation (1):
P=C·V
2
·f
(1)
where C is a load capacitance and V is a power supply voltage.
Additionally, there is another problem that in general, the higher the operational frequency is, the more difficult the circuit design and the layout design are.
Recently, a demand for a semiconductor memory exhibiting a low power consumption and a high data transfer speed at the same time has been increased with the prevalence of mobile devices, the large-scaling of systems, the reduction of required power source voltage, and the spread of applications to image processing and the like.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory, which has a wide bus-bandwidth, and enables low power consumption at the same time.
It is another object of the present invention to provide a semiconductor memory, which shortens access time.
According to one of the aspects of the semiconductor memory of the present invention, the semiconductor memory has a plurality of memory cells, a plurality of bit lines respectively connected to the memory cells, a plurality of sense amplifiers respectively connected to the bit lines, and a data control circuit. For example, during a read operation, the data read from the memory cells onto the bit lines are amplified simultaneously by the sense amplifiers and outputted to the exterior of the memory. In this read operation, the data control circuit outputs all the data read from the memory cells and amplified simultaneously by the sense amplifiers to the exterior. During a write operation, the data supplied from the exterior to the bit lines are amplified simultaneously by the sense amplifiers and written into the memory cells. In this write operation, the data control circuit writes into the memory cells all the data inputted from the exterior and amplified simultaneously by the sense amplifiers. Since all the data amplified simultaneously by the sense amplifiers are inputted/outputted from/to the exterior, the data transfer rate of inputted/outputted data can be increased, and the power consumption per unit amount of transferred data can be reduced.
According to another aspect of the semiconductor memory of the present invention, a plurality of data bus lines are respectively formed corresponding to the bit lines for inputting/outputting the data from/to the exterior. Since the data amplified simultaneously by the sense amplifiers can be inputted/outputted in parallel via the data bus lines, the data transfer rate can be increased by using a simple control circuit.
According to another aspect of the semiconductor memory of the present invention, the data bus lines are wired along a wiring direction of the bit lines. This facilitates the wiring layout of the data bus lines.
According to another aspect of the semiconductor memory of the present invention, the data bus lines are formed by using wiring layer(s) different from a wiring layer of the bit lines. A wiring pitch of the data bus lines is equal to an integral multiple of a wiring pitch of the bit lines. The wiring is aligned by having the wiring pitch of the data bus lines equal to an integral multiple of the wiring pitch of the bit lines. Therefore, this harmonization in the wiring pitches between the bit lines and the data bus lines allows many wires to be efficiently arranged.
According to another aspect of the semiconductor memory of the present invention, the data bus lines are composed of read data bus lines for transferring the data read from the memory cells and write data bus lines for transferring the
Kitamoto Ayako
Matsumiya Masato
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Lam David
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