Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-06-14
2001-07-31
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S194000, C365S233100
Reexamination Certificate
active
06269034
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory, or more particularly, to a semiconductor memory having a redundancy circuit.
2. Description of the Related Art
A redundancy circuit is used to replace a defective cell included in a memory, or especially, a dynamic RAM with a redundancy cell.
For preventing establishment of a multiword state, in which both a normal word line and a redundancy word line are activated, during such replacement of a defective cell, activation of a normal word line is retarded until it is judged whichever of a redundancy word line and the normal word line should be activated. In recent years, it has been requested to shorten a time interval from the instant an address is supplied to the instant data stored in memory cell is read out based on the address.
FIG. 8
is a circuit diagram showing an example of a related art circuit.
FIG. 9
is a timing chart showing the waveforms of signals produced in the circuitry.
First, external address signals A
0
to Aj are stored in row address buffers
110
. The row address buffers
110
acquire the external address signals A
0
to Aj at the leading edge of an external address latching signal ECLK. Row address signals XA
0
to XAj output from the row address buffers
110
are input to an address judgment circuit
130
and address pre-decoders
120
. The address judgment circuit
130
compares the row address signals XA
0
to XAj with a pre-set address in response to a redundancy latching signal. If the row address signals XA
0
to XAj agree with the pre-set address, a redundancy judgment signal AC remains active (solid line in AC in FIG.
9
). If the row address signals XA
0
to XAj disagree with the pre-set address, the redundancy judgment signal AC is inactive (dashed line in AC in FIG.
9
). A redundancy control circuit
140
reads the redundancy judgment signal AC at the leading edge of a row address latching signal RCLK′ after address judgment is completed, and then judges whether a redundancy word line should be activated. At this time, an address pre-decoder
120
acquires signals resulting from pre-decoding of the row address signals XA
0
to XAj and outputs address pre-decoded signals PXA
0
to PXAk to a normal word decoder
160
. Either of a normal word line and a redundancy word line is activated based on a redundancy word enabling signal RDC and a normal word enabling signal XDES that are output signals of the redundancy control circuit
140
.
According to the related art shown in FIG.
8
and
FIG. 9
, for preventing establishment of a multiword state, both the normal word decoder
160
and redundancy word decoder
150
are held unselected until a time instant when it is judged whichever of a normal word line and a redundancy word line should be activated. After the judgment is made, the row address latching signal RCLK′, which is a delayed row address latching signal, is driven high, and either of the normal word decoder
160
and redundancy word decoder
150
is selected. For example, The redundancy control circuit produces the signal XDES of a low logic level at first. Then, the redundancy control circuit changes the level of the signal XDES from the low logic level to a high logic level when the redundancy control circuit receives the rising edge of the signal RCLK′ and the signal AC indicating that an addressed memory cell is not a defective cell. On the other hand, the normal word line decoder does not select any normal word lines at all when the normal word line decoder receives the signal XDES of the low logic level. The normal word line decoder selects one of the normal word lines in response to the address PXA
0
~PXAk after the level of the signal XDES changes from the low logic level to the high logic level. The time required for activating a normal word line is therefore dependent on the normal word enabling signal XDES indicating the results of the judgment. However, the number of normal word lines is larger than the number of redundancy word lines. The number of stages of logic circuits included in the normal word decoder
160
is much larger than that included in the redundancy word decoder
150
. As shown in
FIG. 9
, it takes much time to activate a normal word line. Quick access to a memory cell has therefore been disabled in the past.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory having a redundancy circuit, which can activate a normal word line earlier as well as prevent a multiword movement.
another object of the present invention is to provide a semiconductor memory which improves an access speed.
According to the present invention, there is provided a semiconductor memory including normal memory cells, redundancy memory cells, normal word lines, redundancy word lines, a normal word line selecting/driving means, an address judging means, and a control means. The redundancy memory cells are intended to redress a defect occurring in a normal memory cell. The normal memory cells are selected over the normal word lines. The redundancy memory cells are selected over the redundancy word lines. The normal word line selecting/driving means selects and drives a normal word line in response to externally fed address signals. The address judging means judges whether the address signals represent the address of a defective normal memory cell. Based on the results of judgment output from the address judging means, the control means activates one of a normal word line and a redundancy word line and inactivates the other word line. In an initial state, irrespective of the results of judgment output from the address judging means, a normal word line is activated and a redundancy word line is inactivated. When the judging means judges that the address signals represent the defective address, the control means inactivates the normal word line and activates the redundancy word line.
According to the present invention, there is provided a semiconductor memory comprising normal memory cells, redundancy memory cells, a normal word decoder, and a redundancy word decoder. The redundancy memory cells are intended to redress a defect occurring in a normal memory cell. The normal word decoder selects and drives a normal memory cell. The redundancy word decoder selects and drives a redundancy memory cell. The semiconductor memory further comprises address pre-decoders, an address judgment circuit, and a redundancy control circuit. The address pre-decoders acquire row address signals fed externally synchronously with a first clock signal, decode the signals, and transfer the resultant pre-decoded signals to the normal word decoder. The address judgment circuit judges whether the row address signals represent the address of a defective normal memory cell. The redundancy control circuit acquires the results of judgment output from the address judgment circuit synchronously with a second clock signal, and transfers the results of judgment to the redundancy word decoder. If the results of judgment demonstrate that the address signals represent the defective address, the redundancy control circuit outputs a control signal used to inactivate the normal word decoder. If the results of judgment demonstrate that the address signals do not represent the defective address, the redundancy control circuit outputs a control signal used to activate the normal word decoder.
In this case, the first clock signal makes a transition prior to output of the results of judgment from the address judgment circuit. The second clock signal makes a transition prior to transfer of the pre-decoded signals to the normal word decoder.
The second clock signal is produced by delaying the first clock signal by a predetermined time interval.
Moreover, according to the present invention, there is provided a semiconductor memory including normal memory cells, redundancy memory cells, a normal word decoder, a redundancy word decoder, an address judgment circuit, a redundancy control circuit, and a selecting means. The
Ho Hoai V.
McGinn & Gibb PLLC
NEC Corporation
LandOfFree
Semiconductor memory having a redundancy judgment circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory having a redundancy judgment circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory having a redundancy judgment circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2530117