Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2001-08-08
2003-05-27
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S230010, C365S230060
Reexamination Certificate
active
06570793
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a redundancy circuit for a semiconductor memory which has a memory cell matrix whose memory cells are selected by word lines and bit lines, the word lines contain redundant word lines which are activated when a word line is defective, and a method for activating word lines with such a redundancy circuit.
Semiconductor memories in which data can be stored after an address has been preset and read out again at the address are generally organized in blocks. Here, each memory block has a number of memory cells which can be selected by word lines and bit lines. In the case of dynamic memories with random access (DRAMs), 1-transistor memory cells are usually used in which a memory capacitor is connected to a bit line via a selector transistor. The selector transistor is also connected to a word line via a control terminal. The word lines and bit lines are disposed in the form of a matrix, the memory cells being located at the points of intersection. Each memory block is bounded on two opposite sides by sense amplifiers.
The DRAMs are driven in such a way that only one word line per memory block is selected at a given time because otherwise a plurality of memories would be connected simultaneously to the same bit line.
In order to repair faulty memory cells in such semiconductor memories, the word lines with the defective memory cells are replaced by redundant word lines with intact memory cells which are connected to the same bit lines. Here, the procedure is generally such that, when a line address for addressing a defective word line is applied, the word line that is redundant with respect thereto is selected and the defective word line is prevented from being activated. During the redundancy programming, two methods are customary here. In what is referred to as intra-block redundancy, a defective word line is replaced by a word line, which is redundant with respect thereto and is provided in the same memory block.
This ensures that, even when a defective word line is replaced, there is always at most one word line active within a memory cell block. However, a disadvantage with intra-block redundancy is that it is necessary to provide a very large number of redundant word lines, and thus memory cells per block. For this reason, instead of intra-block redundancy, inter-block redundancy methods are also used in which a defective word line in a memory block is replaced by a redundant word line in another memory block.
In the known redundancy circuits, the redundancy programming is carried out in such a way that, if an address signal with a line address is applied to the DRAM, the address is tested by a comparator device in the redundancy circuit in order to determine whether the applied line address is the address of a defective word line. This can occur, for example, in such a way that the output signals of fuse sets are evaluated in the DRAM which, when there is a defective word line in a memory block, makes it possible to activate a word line which is redundant with respect thereto in the same memory block, or in another memory block. If the evaluation of the fuse sets indicates correspondence between the applied line address and a fused line address, the comparator device of the redundancy circuit then generates an activation signal that activates the associated redundant word line via a respective driver. If the comparator device of the redundancy circuit determines that the applied line address is, however, not a fused line address, an activation signal is output to an address decoding device in the redundancy circuit, which decodes the applied line address and then activates the associated word line by the respective driver.
U.S. Pat. No. 5,894,441 discloses a redundancy circuit for a semiconductor memory. In this redundancy circuit, an address signal with a line address is applied in parallel to a comparator device of the redundancy circuit and to the address-decoding device. If the evaluation of a fuse set of the comparator device reveals that there is a correspondence between the applied line address and a fused line address, an activation signal for a respective driver of the associated redundant word line is generated by the comparator device of the redundancy circuit. At the same time, the comparator device of the redundancy circuit outputs a deactivation signal to an address-decoding device in order to prevent the latter from activating the defective word line by a respective driver.
The known redundancy circuits provide a chronological sequence for the activation of word lines. When a line address signal is applied, a comparator device of the redundancy circuit tests whether the address is that of a defective word line. This requires a certain testing period. If a defective word line is detected, the word line, which is redundant with respect thereto is subsequently activated with an activation signal, which then changes from a low level to a relatively high level. If, on the other hand, the comparator device of the redundancy circuit determines that the applied address characterizes an intact word line, an activation signal is output to the address decoding circuit, when then activates the respective word line after a delay time. The word line is then switched from the low level to the high level.
A disadvantage with the conventional word line activation method is that when an intact word line is activated it is necessary to wait for the redundancy evaluation, which leads to an undesired loss of access time to the intact word line.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a semiconductor memory having a redundancy circuit for word lines and a method for operating the memory that overcome the above-mentioned disadvantages of the prior art methods and devices of this general type, which are distinguished by reliable redundancy testing accompanied by rapid access to the word line to be activated.
With the foregoing and other objects in view there is provided, in accordance with the invention, a redundancy circuit for a semiconductor memory having a memory cell matrix with memory cells, word lines and bit lines for selecting the memory cells. The word lines include redundant word lines activated when one of the word lines is defective. The redundancy circuit contains an address decoding device for decoding an applied address for a word line and activating the word line associated with the applied address. A redundancy comparator device is provided for testing the applied address for the word line to determine whether the word line has an address of a defective word line. After the applied address has been determined as being the address of the defective word line, the redundancy comparator device activates a respective redundant word line. The redundancy comparator device has an output device connected to the address decoding device and the output device outputs a deactivation signal after the applied address for the word line has been determined as being the address of the defective word line. The address decoding device and the redundancy comparator device are configured such that the address decoding device decodes the applied address for the word line in a chronologically parallel fashion and activates the word line associated with the applied address. The redundancy comparator device tests the applied address for the word line to determine whether the word line is the defective word line. The address decoding device has a deactivation device for deactivating the word line being an activated defective word line after a reception of the deactivation signal from the redundancy comparator device.
The redundancy testing according to the invention is distinguished by the fact that a redundancy comparator device is used to test an applied address for a word line to determine whether it is the address of a defective word line, and at the same time an address decoding device activates the respective word line. If it is determined during the checking of the appl
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Nguyen Viet Q.
Stemer Werner H.
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