Semiconductor memory having a pillar type trench dram cell

Details Semiconductor memory having a pillar type trench dram cell Semiconductor memory having a pillar type trench dram cell

2005-02-22

2005-02-22

Weiss, Howard (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S242000

Reexamination Certificate

active

06858893

ABSTRACT:
A semiconductor memory includes a silicon substrate having a cell array region wherein plural rectangular silicon pillars are formed in rows and columns by a trench having a width of1aand formed in a lattice form, a storage node formed on at least a surface of a lower portion of the silicon pillar, a well region formed in an upper half above the storage node, a diffusion layer formed on an upper surface of the well region, a capacitor dielectric formed on the storage node to surround the lower portion of the silicon pillar, a plate electrode buried in the lower portion of the trench to substantially the same level as the upper end of the storage node, and a first gate electrode formed on the channel portion via a first gate insulator.

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Bryant, A., et al. “Characteristics of CMOS Device Isolation for the ULSI Age”, Dec. 1994, IEDM, pp. 671-674.

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