Semiconductor memory having a dummy signal line connected to...

Details Semiconductor memory having a dummy signal line connected to... Semiconductor memory having a dummy signal line connected to...

2007-02-16

2008-09-02

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Read/write circuit

Testing

C365S191000, C365S203000, C365S210100

Reexamination Certificate

active

07420860

ABSTRACT:
First dummy memory cells connected to a first dummy signal line have the same shape and characteristics as those of a real memory cell. The first dummy memory cells are arranged to be adjacent to outermost real memory cells. A voltage setting circuit changes the voltage of the first dummy signal line from a first voltage to a second voltage in order to write test data onto the first dummy memory cell during a test mode. By writing data of a logic opposite to that of the test data onto the real memory cell adjacent to the first dummy memory cell by means of an operation control circuit, a leak failure that may occur between the first dummy memory cell and the real memory cell adjacent thereto can be checked.

REFERENCES:
patent: 6337814 (2002-01-01), Tanida et al.
patent: 6580649 (2003-06-01), Park
patent: 6839293 (2005-01-01), Kawamoto et al.
patent: 2000-207899 (2000-07-01), None
patent: 2001-351399 (2001-12-01), None

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