Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2002-01-15
2003-06-24
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S233100, C365S189050
Reexamination Certificate
active
06584021
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a semiconductor memory having a memory cell array which includes dynamic memory cells. The semiconductor memory has various operating states. A delay locked loop converts an input clock signal into a delayed output clock signal. On the basis of this delayed output clock signal, data values are provided in a clocked manner at an output connection.
Synchronously operating semiconductor memories, in particular SDRAMs (Synchronous Dynamic Random Access Memories), are operated cyclically, i.e. in a clocked manner. The data values read from the memory are available in sync with a clock signal applied to the semiconductor memory externally. In the case of DDR SDRAMs (DDR: Double Data Rate), a data value may be available both on the rising edge and on the falling edge.
Signal paths and switching stages inside chips mean that operating clocks derived from externally supplied clock signals have different phase relationships with respect to the supplied clock signal at different points within the semiconductor memory. A critical factor is the actuation of the data output driver, to which, according to the standardized specification, the data value which is to be output needs to be applied in sync with the clock signal supplied at another point. For this reason, the semiconductor memory contains a delay locked loop which ensures that the clock signal controlling the output driver is available in sync with the externally applied clock signal, and, in particular, the edges of the output data signal match the edges of the supplied clock signal. The delay locked loop uses a suitable control loop to delay a clock signal derived from the external clock signal such that the clock edges controlling the data output driver synchronously match the clock edges of the external clock signal.
The delay times inside a chip vary during operation. By way of example, temperature changes may arise which may be caused by changing ambient temperature or the change from standby mode to normal mode with a relatively high consumed power loss. To be able to continue to provide the output data in sync with the externally supplied clock signal, it is necessary to adjust the delay produced by the delay locked loop.
The application note “Committee Letter Ballot”, JC-42.3-99-081, Item 986, May 10, 1999 issued by the standardization committee JEDEC (Joint Electronic Devices Engineering Council) Solid State Technology Association proposes adjusting the delay locked loop during a cycle for refreshing the dynamic memory cells (Autorefresh). Since refresh cycles require up to 15.6 &mgr;s, great demands need to be made one the thermal stability of the delay locked loop. One problem is that, in particular operating states, the demands on the synchronism of the data which are output may be violated.
U.S. Pat. No. 5,990,730 describes a semiconductor memory in which the delay time of a delay locked loop can be adjusted. Immediately after the supply voltage has been applied, the delay time of a delay locked loop is finely adjusted on the basis of a test current produced from the semiconductor memory. The adjustment process is ended again immediately after the supply voltage has been applied, and the adjustment then remains unchanged.
U.S. Pat. No. 6,080,255 describes a semiconductor memory in which the delay time of a delay locked loop is altered in steps of different size. The size of the steps is chosen on the basis of the operating state in order to achieve the locked state as quickly as possible when changing over from standby mode to normal mode.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a semiconductor memory which overcomes the above-mentioned disadvantages of the heretofore-known semiconductor memories of this general type and which has an increased operational reliability with the lowest possible circuit complexity. In particular, it should be possible to provide the output data using synchronous timing under as many operating conditions as possible, always adhering to the demanded specification.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor memory, including:
a memory cell array including dynamic memory cells;
an output connection operatively connected to the memory cell array for outputting data values stored in the dynamic memory cells;
a state machine selectively having an operating state Read, Write or Refresh and having a signal connection providing a control signal for displaying the operating state Read;
a delay locked loop operatively connected to the state machine, the delay locked loop receiving an input clock signal and providing a delayed output clock signal, the delay locked loop having a signal connection for receiving the control signal from the state machine, the delay locked loop being configured to be actuated by the control signal in order to suppress a change in a delay time between the input clock signal and the delayed output clock signal during the operating state Read; and
an output driver operatively connected to the delay locked loop, the output driver being configured to be actuated by the delayed output clock signal in order to provide, at the output connection, data values read from the dynamic memory cells in sync with the delayed output clock signal.
In other words, the object of the invention is achieved through the use of a semiconductor memory including: a memory cell array containing dynamic memory cells; a state machine which has one of the operating states Read, Write and Refresh, and a signal connection with a control signal applied to it in order to display the operating state Read; a delay locked loop to whose input an input clock signal can be supplied and which produces a delayed output clock signal; an output driver which can be actuated by the delayed output clock signal in order to provide data values read from the memory cells in the memory cell array at an output connection of the semiconductor memory in sync with the output clock signal; a signal connection for the delay locked loop, which can be actuated by the control signal produced by the state machine in order to suppress altering the delay time between the input clock signal and the delayed output clock signal from the delay locked loop during the operating state Read.
In the semiconductor memory according to the invention, the delay locked loop can be adjusted in all operating states except in the Read mode. Readjustment of the clock signal controlling the output driver on the basis of changes in the delay characteristics within the semiconductor memory is therefore possible more often than in the above-mentioned application note from JEDEC. This means that the delay locked loop can be matched more closely to the synchronism stipulated by the clock signal applied to the semiconductor memory externally. Changes in the delay time of the internal switching stages on account of rapid changes in temperature can also be compensated for. Nevertheless, there is the assurance that the delay locked loop is not adjusted when data values are being output, in order to prevent sudden phase changes during data output.
The output buffer controlled cyclically, i.e. in a clocked manner, by the delay locked loop is connected to the data signal path which provides the data stored in the memory cell array of the semiconductor memory. The output buffer provides the data either on the rising edge (according to SDRAM standard) or on the rising and falling edges (according to DDR SDRAM standard).
The memory cells in the semiconductor memory are dynamic memory cells which lose the stored charge, representing the data value to be stored, on account of leakage currents. Such memory cells include a transistor for selecting the memory cell and a capacitor for storing charge. To compensate for the charge losses in the storage capacitor, a refresh cycle is performed which reads the data content of the memory cells and accordingly reinforces the stored quantity of cha
Hein Thomas
Heyne Patrick
Partsch Torsten
Thilo Marx
Greenberg Laurence A.
Hoang Huan
Infineon - Technologies AG
Mayback Gregory L.
Stemer Werner H.
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