Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2002-08-05
2004-11-16
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S195000, C365S230060, C365S230080, C365S238500
Reexamination Certificate
active
06819604
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory, and more specifically to a method for relieving a defective memory cell and a semiconductor memory incorporating therein a circuit for relieving a defective memory cell.
In a process for fabricating a semiconductor memory, defective memory cells occur often, and if the defective memory cells are fount out in an inspecting step, even if only one bit is defective, the whole of the memory chip is rejected. Therefore, particularly, in a semiconductor memory having a large memory capacity, redundant memory cells are previously provided to relieve the defective cells. In order to relieve the defective cells, it is necessary to provide on a chip a non-volatile memory for storing information for substituting a nondefective redundant memory cell for the defective memory cell found out in a chip test time.
In the prior art, in many cases, a memory of the information for substituting the nondefective redundant memory cell for the defective memory cell, is realized by a fuse (whether or not the fuse is broken) provided in the semiconductor memory.
Alternatively, a relief circuit has been proposed which uses a ferroelectric capacitor in place of the fuse. The relief circuit using a ferroelectric capacitor is disclosed by for example JP-A-2000-215687 or JP-A-09-128991.
Now, the redundant relief circuit disclosed in JP-A-09-128991 will be described with reference to
FIGS. 22 and 23
. In
FIG. 22
, an address signal supplied from an external of the chip is inputted to a row decoder
2205
and a column decoder
2202
, and then, supplied to defective memory cell relief circuits
2206
and
2203
. When a memory cell designated by the given address is a defective memory cell, an address translation is carried out by the defective memory cell relief circuits
2206
and
2203
, so that a nondefective redundant memory cell is accessed.
FIG. 23
illustrates the defective memory cell relief circuit. In
FIG. 23
, a relief address storing circuit
2302
is constituted of “n+1” ferroelectric memory cells. The ferroelectric memory cell FE is constituted of one nMOS transistor and one ferroelectric capacitor. The relief address storing circuit
2302
stores an address of “n” bits and information of one bit indicative of substitution or nonsubstitution. A relief address writing circuit
2301
is used for writing a substitution information into the relief address storing circuit
2302
.
A relief address reading circuit
2303
reads the substitution information from the relief address storing circuit
2302
and supplies the read-out substitution information into a redundant decoder
2310
.
The redundant decoder
2310
compares the read-out substitution information with the address inputted to the chip. When coincidence is obtained, namely, when the address is replaced by another, the redundant decoder
2310
selects a redundant memory cell. On the other hand, when coincidence is not obtained, the redundant decoder
2310
allows a memory cell designated by the inputted address to be selected.
The redundant relief circuit disclosed in the above referred JP-A-09-128991 can reduce the number of steps in the test time, in comparison with the prior art relief address storing circuit using the fuse, since a trimmer or the like is not used, and since an electrical writing is possible. In addition, the redundant relief circuit disclosed in JP-A-09-128991 can reduce an occupying area for the whole of the relief circuit.
On the other hand, the above referred JP-A-2000-215687 discloses a memory device having a defective memory cell relief circuit in particular for a ferroelectric memory (FeRAM), in which a redundant file memory for storing the substitution information indicative of whether or not it is a defective cell to be replaced by a redundant cell, is constituted of memory cells having the same arrangement as that of main memory cells, and the redundant file memory is accessed as the same time as the main memory cells are accessed, so that a substitution information stored in the redundant file memory is read out when the main memory cells are accessed, and the defective memory cell is replaced by the redundant cell in accordance with the substitution information.
This memory device will be described with reference to FIG.
24
. In
FIG. 24
, each of columns COL
0
to COL
7
and RCOL is constituted to have 8 bit line pairs. Substitution is carried out in units of column. The substitution information is stored in ferroelectric memory cells, which are located in the same word lines as those of the main memory cells.
The substitution information is read out as the same time as the main memory cells are accessed. The read-out substitution information is compared with the column address inputted, and when coincidence is obtained, redundant memory cells (of 8 bits since it is in units of column) is selected.
Since the substitution information storing cells are arranged in the same manner as that of the main memory cells, a writing/reading circuit can be shared with the main memory cells, so that a construction can be simplified. In addition, since the writing/reading operation of the main memory cells is the same as that of the substitution information storing cells, the testing becomes easy, and it is possible to write the substitution information after packaged. Furthermore, since the substitution information storing cells are arranged in the same word lines as those of the main memory cells, it is possible to set the substitution information of the defective memory cells in units of word line, and therefore, the degree of substitution is very high.
Incidentally, JP-A-2000-067594 discloses a non-volatile semiconductor memory device having a latch circuit latching, at a power-on time, an address data of a defective address storing part which stores an address of a defective memory cell.
However, the arrangement disclosed in the above referred JP-A-09-128991 so configured to store the substitution information by action of the ferroelectric memory cells is disadvantageous in that the whole of the relief circuit needs a large area and the access time becomes long. In other words, since the fuses are replaced with the ferroelectric memory cells, the area for the fuses becomes greatly reduced. However, a dedicated writing/reading circuit becomes necessary, and further, it is necessary to provide on the chip a pad or pads for supplying data to written. The overhead of the chip area attributable to the installation of the relief circuit cannot become so small.
In addition, in order to replace the defective memory cell, the address inputted to the chip is supplied to the defective memory relief circuit once, so that the address comparison is carried out within the defective memory relief circuit, and then, if the inputted address is to be replaced, the address translation is carried out, and thereafter, a redundant memory cell is selected finally. Therefore, the access time becomes long.
On the other hand, the memory device disclosed in the above referred JP-A-2000-215687 is also disadvantageous in the chip area and in the access time. In addition, it has another problem in which the characteristics of the ferroelectric capacitor is deteriorated. Namely, in this prior art construction, the substitution information storing cells are located in the same array and in the same word lines as those of the main memory cells, and the substitution information stores the column address of the defective memory cells. In the case that the memory cell array is constituted of 8 columns (8 bit line pairs×8 columns=64 bit line pairs), the redundant memory cells are organized in one column (8 bits), and therefore, at least three bits are required to indicate the column address, and a bit indicative of substitution or nonsubstitution is required, so that at least four bits are required in total. Accordingly, only in the memory cell array excluding a peripheral circuit for the substitution, the area overhead reaches 18% or more. Namely, the a
NEC Corporation
Nelms David
Pham Ly Duy
Sughrue & Mion, PLLC
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