Semiconductor memory having a bypassable data output latch

Details Semiconductor memory having a bypassable data output latch Semiconductor memory having a bypassable data output latch

1985-12-26

1988-08-23

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

For complementary information

365233, 365189, G11C 700, G11C 800

Patent

active

047665726

ABSTRACT:
A semiconductor memory is disclosed which attains a data read operation at a high speed with a low power dissipation. The memory includes a sense amplifier amplifying a data signal stored in the selected memory cell, a data latch circuit latching the output signal of the sense amplifier, a switching circuit outputting the output signal of the sense amplifier before the data latch circuit latches the output signal of the sense amplifier and outputting the output signal of the data latch circuit after the data latch circuit latches the output signal of the sense amplifier, and an output circuit producing an output data signal responsive to the output signal of the switching circuit.

REFERENCES:
patent: 4060794 (1977-11-01), Feldman et al.
patent: 4366556 (1982-12-01), Kyomasu et al.
patent: 4415994 (1983-11-01), Ive et al.
patent: 4573147 (1986-02-01), Aoyama et al.
patent: 4603403 (1986-07-01), Toda
patent: 4616341 (1986-10-01), Andersen et al.

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