Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1981-08-12
1984-07-31
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Bad bit
371 10, G11C 1140
Patent
active
044634501
ABSTRACT:
A semiconductor memory has a plurality of modules or boards each with a plurality of memory integrated circuits and redundant memory areas. For receiving of information for replacement circuiting of faulty bit locations in a memory circuit with redundant memory areas, a volatile auxiliary memory is provided in the memory circuit. Each structural unit, which is easily exchangeable in the course of maintenance jobs which encompass a plurality of memory circuits such as a printed circuit board, has associated with it a programmable non-volatile read-only memory for receiving the replacement circuit information for all memory circuits which are combined in the structural unit. The programming of the read-only memory preferably proceeds during testing of the structural unit.
REFERENCES:
patent: 3755791 (1973-08-01), Arzubi
patent: 4047163 (1977-09-01), Choate et al.
IBM Technical Disclosure Bulletin, vol. 15, No. 6, Nov. 1972, W. F. Beausoleil, "Utilization of Defective Memory Chips by Substituting Redundant Words for Defective Words".
IBM Technical Disclosure Bulletin, vol. 25, No. 3A, Aug. 1982, Chan et al., "Array Word Redundancy Scheme".
Japanese Laid-Open Application No. 52-33431, Mar. 1977.
"Multiple Word/Bit Line Redundancy for Semiconductor Memories", by Stanley Schuster, IEEE Journal of Solid-State Circuits, vol. SC13, No. 5, Oct. 1978, pp. 698-703.
"Memory Data Book and A Designers Guide", Publication of Mostek Corp., Carollton, U.S.A., Feb. 1978, pp. 107-116, Module MK4116.
Popek Joseph A.
Siemens Aktiengesellschaft
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