Semiconductor memory for relieving a defective bit

Static information storage and retrieval – Read/write circuit – Bad bit

Reexamination Certificate

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C365S185090, C365S210100

Reexamination Certificate

active

07623399

ABSTRACT:
A semiconductor memory has a memory unit including a regular cell array having a plurality of memory cells and a decoder for decoding an input address and selecting a memory cell corresponding to the input address in the regular cell array, in which an access operation is performed to the selected memory cell; a defective address storage section which stores a defective address corresponding to a defective bit in the regular cell array; and a replacement address storage section which stores a replacement address corresponding to a replacement bit in the regular cell array. When a supply address supplied to the memory unit matches the defective address, the replacement address, in place of the supply address, is supplied to the memory unit as the input address, according to which the access operation is performed.

REFERENCES:
patent: 5657281 (1997-08-01), Rao
patent: 6202180 (2001-03-01), Nose
patent: 6212118 (2001-04-01), Fujita
patent: 6414885 (2002-07-01), Nagamatsu et al.
patent: 2-206286 (1990-08-01), None
patent: 5-189327 (1993-07-01), None
patent: 11-7761 (1999-01-01), None
patent: 2001-189094 (2001-07-01), None
patent: 57-064395 (2002-04-01), None
patent: 2002-298596 (2002-10-01), None

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