Semiconductor memory for operation in a plurality of...

Details Semiconductor memory for operation in a plurality of... Semiconductor memory for operation in a plurality of...

1999-03-05

2002-11-26

Thai, Tuan V. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S100000, C711S154000

Reexamination Certificate

active

06487629

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates to a semiconductor memory, and more particularly, to set-up of a mode of operation of a semiconductor device.
A synchronous graphic RAM (SGRAM) is used to efficiently process of large amounts of data, such as image data. The SGRAM operates in a number of operational modes which allow it to perform rapid data processing. These modes include a burst mode, a block write mode and the like. The burst operation refers to a read/write operation with respect to a memory core in which information is sequentially accessed by specifying a plurality of column addresses. The block write operation performs a data write operation into a plurality of memory cells using a plurality of column select signals.
Referring to
FIG. 1
, a conventional SGRAM
10
formed on a single semiconductor substrate, such as a single crystal silicon substrate using a known semiconductor integrated circuit manufacturing technology is known. The SGRAM
10
is connected to a system
32
which provides the SGRAM
10
with a variety of signals such as a clock signal CLK, a distribution enable signal CKE, instruction code signals which constitute operation commands, an address signal A
10
-A
0
(where A
10
represents the most significant bit and A
0
the least significant bit), a data signal D
7
-D
0
(where D
7
represents the most significant bit and D
0
the least significant bit), a data mask signal DQM and the like. The SGRAM
10
is controlled in accordance with the various signals from the system
32
in synchronism with the clock signal CLK, in a similar manner as a synchronous DRAM.
The SGRAM
10
includes a memory core
12
, a clock buffer
14
, an instruction decoder
16
, an address buffer register
18
, an input/output (I/O) buffer
20
, a control signal latch
22
and a column address counter
24
. The SGRAM
10
additionally includes operational mode registers such as a mode register
26
, a color register
28
and a mask register
30
, where the color register
28
and the mask register
30
represent special mode registers. Access information, which defines individual operational modes of the SGRAM
10
, is stored or loaded in the mode register
26
, the color register
28
and the mask register
30
.
The memory core
12
has a multitude of dynamic memory cells which are disposed in a matrix array. The memory core
12
is provided with a row decoder and a column decoder, which are known in the art, and a memory cell has a select terminal connected to a word line and a data input terminal connected to a data line.
The clock buffer
14
receives the clock signal CLK (shown in
FIG. 2
) and the distribution enable signal CKE from the system
32
. In response to the distribution enable signal CKE of a high level (or logical “1” level), the clock buffer
14
provides the clock signal CLK to the instruction decoder
16
, the address buffer register
18
and the I/O buffer
20
.
A summary of the operation of the SGRAM
10
will be given. An operational mode such as the burst operation, the block write operation or the like is initially set up, and a read/write operation then follows in accordance with the operational mode specified. The system
32
provides an address signal A
10
-A
0
, as access information which specifies the operational mode, to the SGRAM
10
. During the read/write operation, the system
32
provide the address signal A
10
-A
0
to the SGRAM
10
to serve as a row address signal which selects a word line for the memory core
12
and as a column address signal which selects a data line for the memory core
12
. All bits in the address signal A
10
-A
0
are used to form the row address signal. Part of the address signals A
10
-A
0
, for example, eight bits A
7
-A
0
are used as the column address signal. The three most significant bits A
10
-A
8
of the address signal are not used in the selection of a data line.
The address buffer register
18
receives the clock signal CLK from the clock buffer
14
and receives the address signal A
10
-A
0
in synchronism with the clock signal CLK. During the set-up of an operational mode, the address buffer register
18
loads bits A
7
-A
0
of the address signal into the mode register
26
by way of an internal bus as the access information. The access information in the mode register
26
is also provided to the control signal latch
22
. In addition, the address buffer register
18
provides the address signal A
10
-A
0
to the instruction decoder
16
. The most significant bit A
10
of the address signal is used, for example, to designate one of the mode register
26
, the color register
28
and the mask register
30
. During the read/write operation, the address buffer register
18
provides the row address signal A
10
-A
0
to the row decoder via an internal bus and also provides the column address signal A
7
-A
0
to the column address counter
24
.
The column address counter
24
is provided to implement the burst operation. The column address counter
24
includes a burst counter, not shown, which forms a column address signal, and a burst end counter, not shown, which restricts the number of column address signals formed. The column address signal A
7
-A
0
from the address buffer register
18
is loaded into the burst counter as an initial value. The mode register
26
has stored therein a burst length as access information, which is provided to the burst end counter. In this manner, the burst end counter is preset with burst length information, which is then counted down or decremented to produce an underflow signal. The burst counter is incremented from the initial value until the burst end counter underflows, thus sequentially producing column address signals. The column address signal produced in this manner is decoded by the column decoder within the memory core
12
into a select signal for a particular data line. Data write-in or data read-out into or from a selected memory cell then takes place. After having produced a number of column address signals which depends on the burst length information, the column address counter
24
produces an internal trigger signal TR which indicates the end of the column address signals.
The I/O buffer
20
receives the clock signal CLK from the clock buffer
14
and receives the data signal D
7
-D
0
from the system
32
in accordance with the clock signal CLK. In addition, the I/O buffer
20
delivers the data signal D
7
-D
0
which is read from the memory core
12
to the system
12
in accordance with the clock signal CLK. During the set-up of the operational mode, if either the color register
28
or the mask register
30
is selected, the I/O buffer
20
loads the data signal D
7
-D
0
into the color register
28
or the mask register
30
as access information. During the write operation, the I/O buffer
20
feeds the data signal D
7
-D
0
to the memory core
12
. The data signal D
7
-D
0
from the I/O buffer
20
is amplified by a write amplifier, not shown, before it is transmitted onto the data line in the memory core
12
and then that the transmitted signal is written into selected memory cells. During the read operation, data signal D
7
-D
0
from the data line in the memory core
12
is amplified in by main amplifier, not shown, and then delivered by the I/O buffer
20
to the system
32
. During the burst operation, the I/O buffer
20
receives one column address from the system
32
, and sequentially produces a predetermined number of column address signals inclusive of the received one, which consecutively follow the received column address signal for performing a read/write operation.
The mode register
26
includes a plurality of identically constructed registers, not shown, which correspond to the address signal A
10
-A
0
. Access information is loaded into the mode register
26
in accordance with control signals fed from the control signal latch
22
. The control signal latch
22
produces control signals for the mode register
26
in response to a predetermined status signal from the instruction decoder
16
. For example, the

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