Semiconductor memory element and semiconductor memory device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257391, 365104, H01L 2978

Patent

active

054263212

ABSTRACT:
The present invention relates to a semiconductor memory device having a planner cell structure. A source with a large area is formed on a P-type silicon substrate, a plurality of strip-like word lines are formed in parallel to each other on the source, gate oxide films are formed on both side walls of each of the word lines, and an epitaxial layer is formed between the word lines. A plurality of strip-like bit lines are formed in parallel to each other perpendicularly to the word lines on the oxide film, and the epitaxial layer, and a drain is formed in the epitaxial layer under a polycrystalline silicon film of the bit line. A channel is formed in contact with the gate oxide film between the drain and the source in the epitaxial layer, and an electric current flows in a longitudinal direction when a memory element becomes ON.

REFERENCES:
patent: 4663644 (1987-05-01), Shimizu
patent: 5306941 (1994-04-01), Yoshida

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