Semiconductor memory devices with spare column decoder

Static information storage and retrieval – Read/write circuit – Bad bit

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36523006, 36518904, 36518907, G11C 700

Patent

active

059264217

ABSTRACT:
Disclosed is a semiconductor memory device having a plurality of memory cell arrays made of normal column cell arrays and spare column cell arrays, and a global column decoder for simultaneously selecting normal column lines of the memory cell array, wherein spare column decoders for selecting spare column lines of each spare column cell array are respectively and independently formed in the spare column cell arrays.

REFERENCES:
patent: 5469401 (1995-11-01), Gillingham
patent: 5488585 (1996-01-01), Kim
patent: 5504712 (1996-04-01), Conan
patent: 5544113 (1996-08-01), Kirihata et al.
patent: 5561636 (1996-10-01), Kirihata et al.
patent: 5708619 (1998-01-01), Gillingham

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