Semiconductor memory devices including different thickness...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor

Reexamination Certificate

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C257S339000

Reexamination Certificate

active

06867445

ABSTRACT:
Semiconductor memory devices include memory cell transistors having spaced apart memory cell transistor source and drain regions, and a memory cell transistor insulated gate electrode that includes a memory cell transistor gate dielectric layer. Refresh transistors also are provided that are connected to the memory cell transistor insulated gate electrodes and are configured to selectively apply negative bias to the memory cell transistor insulated gate electrodes in a refresh operation. The refresh transistors include spaced apart refresh transistor source and drain regions, and a refresh transistor insulated gate electrode. The refresh transistor insulated gate electrode includes a refresh transistor gate dielectric layer that is of different thickness that the memory cell transistor gate dielectric layer. The refresh transistor gate dielectric layer may be thinner than the memory cell transistor gate dielectric layer.

REFERENCES:
patent: 6268748 (2001-07-01), Bertin et al.
patent: 20030054613 (2003-03-01), Murakami et al.
patent: 2002-0030702 (2002-04-01), None
Notice to Submit Response, Korean App. No. 10-2002-0040091, Apr. 30, 2004.

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