Semiconductor memory devices having vertically-stacked...

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

Reexamination Certificate

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Details

C365S051000, C365S156000, C365S063000

Reexamination Certificate

active

07978561

ABSTRACT:
Provided is a semiconductor device having transistors of stacked structure. The semiconductor memory device having transistors includes a memory cell array block which includes a plurality of word lines and a plurality of memory cells which each includes at least one first transistor connected between the plurality of word lines, and a word line decoder which includes a plurality of drivers which drive the plurality of word lines, respectively, wherein a plurality of word lines are disposed on a first layer, and a plurality of drivers are disposed on at least two second layers.

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Jung et al., The Revolutionary and Truly 3-Dimensional 25F2SRAM Technology with the smallest S3(Stacked Single-crystal Si) Cell, 0.16um2, and SSTFT (Stacked Single-crystal Thin Film Transistor) for Ultra High Density SRAM, Symposium on VLSI Technology Digest of Technical Papers, 2004, pp. 228-229.
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