Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2011-07-12
2011-07-12
Lam, David (Department: 2827)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S051000, C365S156000, C365S063000
Reexamination Certificate
active
07978561
ABSTRACT:
Provided is a semiconductor device having transistors of stacked structure. The semiconductor memory device having transistors includes a memory cell array block which includes a plurality of word lines and a plurality of memory cells which each includes at least one first transistor connected between the plurality of word lines, and a word line decoder which includes a plurality of drivers which drive the plurality of word lines, respectively, wherein a plurality of word lines are disposed on a first layer, and a plurality of drivers are disposed on at least two second layers.
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Jung et al., The Revolutionary and Truly 3-Dimensional 25F2SRAM Technology with the smallest S3(Stacked Single-crystal Si) Cell, 0.16um2, and SSTFT (Stacked Single-crystal Thin Film Transistor) for Ultra High Density SRAM, Symposium on VLSI Technology Digest of Technical Papers, 2004, pp. 228-229.
Partial European Search Report, European Application No. 05 01 6656, Apr. 13, 2007.
Jung Soon-moon
Lim Hoon
Park Han-Byung
Lam David
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
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