Semiconductor memory devices having a built-in test function

Static information storage and retrieval – Read/write circuit – Testing

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371 212, G06F 1100

Patent

active

058187723

ABSTRACT:
A built-in self-test circuit of semiconductor memory devices comprises a test clock generator that generates a clock for testing during the test of memory cells, a column address counter that gives column addresses, a first and second row-address counters that give row addresses, a data generator/comparator that generates test data and reads out the test data written in memory cells to compare with the test data, a timer that measures a predetermined time period, and a sequencer that controls these circuits wherein the BIST circuit write test data into memory cells in synchronization with the clock for testing, performs disturb for each of the memory cells and reads out the data written in the memory cells to compare the read data with the test data, thereby performing the self-test of the memory cells.

REFERENCES:
patent: 5568437 (1996-10-01), Jamal
patent: 5661729 (1997-08-01), Miyazaki

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