Semiconductor memory devices and signal line arrangements...

Details Semiconductor memory devices and signal line arrangements... Semiconductor memory devices and signal line arrangements...

2007-08-21

2007-08-21

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Interconnection arrangements

C365S149000, C365S230030, C365S230060

Reexamination Certificate

active

11221684

ABSTRACT:
A semiconductor memory device may include a memory cell array, a bit line sense amplifier, a sub word line driver, and an electrode. The memory cell array may include a sub memory cell array connected between sub word lines and bit line pairs and having memory cells which are selected in response to a signal transmitted to the sub word lines and column selecting signal lines. The bit line sense amplifier may be configures to sense and amplify data of the bit line pairs. The sub word line driver may be configured to combine signals transmitted from word selecting signal lines and signals transmitted from main word lines to select the sub word lines. Moreover, the memory cell array may be configured to transmit data between the bit line pairs and local data line pairs and to transmit data between the local data line pairs and global data line pairs. The electrode may be configured to cover the whole memory cell array and to apply a voltage needed for the memory cells. The local data line pairs may be arranged on a first layer above the electrode in the same direction as the sub word line. The column selecting signal lines and the global data line pairs may be arranged on a second layer above the electrode in the same direction as the bit line. The word selecting signal lines and the main word lines may be arranged on a third layer above the electrode in the same direction as the sub word line. Related methods of signal line arrangement are also discussed.

REFERENCES:
patent: 5877981 (1999-03-01), Iwahashi
patent: 6037621 (2000-03-01), Wilson
patent: 6046775 (2000-04-01), Jonnalagadda et al.
patent: 6252898 (2001-06-01), Eto et al.
patent: 6278628 (2001-08-01), Sekiguchi et al.
patent: 6282147 (2001-08-01), Fujima
patent: 04-324190 (1992-11-01), None

Affiliated with

Also associated with

Rating

Semiconductor memory devices and signal line arrangements... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory devices and signal line arrangements..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory devices and signal line arrangements... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3886500