Semiconductor memory devices and methods including coupling...

Details Semiconductor memory devices and methods including coupling... Semiconductor memory devices and methods including coupling...

2002-05-01

2003-09-02

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S063000, C365S189090

Reexamination Certificate

active

06614702

ABSTRACT:

RELATED APPLICATION
This application claims the benefit of Korean Patent Application No. 2001-0038814, filed Jun. 30, 2001, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein.
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor memory devices, and more particularly, to semiconductor memory devices including sense amplifiers and related methods.
Semiconductor memory devices have been developed to provide increased storage capacities, operate at higher speeds, and consume less power. In particular, dynamic random access memories (DRAMs) may include shared bitline sense amplifiers, which are shared by two adjacent memory cell array blocks, and may use a memory cell array power voltage as a shared bitline sense amplifier power voltage. A memory cell array power voltage may be generated by internally reducing an external power voltage applied from outside the memory device.
FIG. 1
is a circuit diagram of a conventional DRAM, and
FIG. 2
is a waveform diagram illustrating the operation of sense amplifiers in the conventional DRAM of FIG.
1
. Referring to
FIG. 1
, bitline sense amplifiers AS
1
through AS
4
are shared by two adjacent memory cell array blocks A
11
and A
13
. Pairs of bitlines ABL
0
i/ABL
0
Bi through ABL
3
i/ABL
3
Bi connected to the first memory cell array block A
11
are equalized to a voltage level AVb
1
by equalization circuits AE
1
through AE
4
. Pairs of bitlines ABL
0
j/ABL
0
Bj through ABL
3
j/ABL
3
Bj connected to the second memory cell array block A
13
are equalized to the voltage level AVbl by equalization circuits AE
5
through AE
8
.
Next, as shown in
FIG. 2
, a first isolation control signal APISOi and a second isolation control signal APISOj reach an external power voltage level AVdd. If the first isolation control signal APISOi reaches a boosting voltage AVpp level and the second isolation control signal APISOj drops to a ground voltage level AVss, pairs of first isolation transistors AT
1
through AT
8
are turned on and pairs of second isolation transistors AT
9
through AT
16
are turned off. In other words, the first memory cell array block A
11
is selected, and the second memory cell array block A
13
is not selected.
Next, a wordline AWL of a memory cell in the first memory cell array block A
11
reaches the boosting voltage level AVpp. If a sense amplifier control signal ALAPG becomes logic ‘low’ and an inverted signal ALANG of the sense amplifier control signal ALAPG becomes logic ‘high’, the sense amplifiers AS
1
through AS
4
start to operate. In other words, a first switch ASW
1
is turned on, and then a memory cell array power voltage AVarray is supplied to a power voltage node ALA of the sense amplifiers AS
1
through AS
4
. Then, a second switch ASW
2
is turned on, and ground voltage AVSS is supplied to a ground voltage node ALAB of the sense amplifiers AS
1
through AS
4
. Then, the sense amplifiers AS
1
through AS
4
sense and amplify the data of the pairs of bitlines ABL
0
i/ABL
0
Bi through ABL
3
i/ABL
3
Bi connected to the first memory cell array block A
11
.
In such a method shown in
FIG. 2
, the pairs of first isolation transistors AT
1
through AT
8
are previously turned on at an early stage of the operation of the sense amplifiers AS
1
through AS
4
by the first isolation control signal APISOi almost reaching the boosting voltage level AVpp, and thus the load of the pairs of bitlines ABL
0
i/ABL
0
Bi through ABL
3
i/ABL
3
Bi connected to the selected memory cell array block (the first memory cell array block A
11
) increases. Accordingly, the operational characteristics of the sense amplifiers AS
1
through AS
4
may deteriorate and the amplification speed of the sense amplifiers AS
1
through AS
4
may be reduced.
FIG. 3
is another waveform diagram illustrating the operation of sense amplifiers of the conventional DRAM shown in FIG.
1
. The method shown in
FIG. 3
may address problems with the method shown in
FIG. 2
discussed above.
In the method shown in
FIG. 3
, the first and second isolation control signals APISOi and APISOj reach the external power voltage level AVdd at an early stage of the operation of the sense amplifiers AS
1
through AS
4
, and then the first isolation control signal APISOi maintains the external power voltage level AVdd and the second isolation control signal APISOj drops to the ground voltage level AVss. The first isolation control signal APISOi reaches the boosting voltage level AVpp at a middle stage of the operation of the sense amplifiers AS
1
through AS
4
.
Accordingly, in the method shown in
FIG. 3
, the pairs of first isolation transistors AT
1
through AT
8
are weakly turned off by the first isolation control signal APISOi at the external power voltage level AVdd, and, thus, the load of the pairs of bitlines ABL
0
i/ABL
0
Bi through ABL
3
i/ABL
3
Bi connected to the selected memory cell array block (the first memory cell array block A
11
) decreases. As a result, the amplification speed of the sense amplifiers AS
1
through AS
4
may be increased using operations shown in FIG.
3
.
However, because the pairs of first isolation transistors AT
1
through AT
8
may not completely turn off at an early stage of the operation of the sense amplifiers AS
1
through AS
4
, the load of the pairs of bitlines ABL
0
i/ABL
0
Bi through ABL
3
i/ABL
3
Bi may not be sufficiently blocked.
SUMMARY OF THE INVENTION
According to embodiments of the present invention, a semiconductor memory device may include a memory cell array comprising a plurality of memory cells, a pair of bit lines coupled to at least one memory cell of the memory cell array, a sense amplifier having a pair of sense amplifier inputs wherein the sense amplifier senses a difference between voltages of the pair of sense amplifier inputs and amplifies the voltage difference, and a pair of isolation switches. More particularly, each isolation switch of the pair can be coupled between one of the pair of bit lines and one of the pair of sense amplifier inputs wherein the pair of isolation switches electrically couples the respective bit lines and the sense amplifier inputs responsive to a coupling signal provided on an isolation control signal line coupled to control electrodes of the isolation switches. In addition, a control switch can be coupled between the isolation control signal line and a power voltage node of the sense amplifier wherein the control switch electrically couples the isolation control signal line to the power voltage node of the sense amplifier during a first period of operation of the sense amplifier for the memory cell.
According to additional embodiments of the present invention, an integrated circuit memory device can include a memory cell array comprising a plurality of memory cells, a pair of bit lines coupled to at least one memory cell of the memory cell array, a sense amplifier having a pair of sense amplifier inputs wherein the sense amplifier senses a difference between voltages of the pair of sense amplifier inputs and amplifies the voltage difference, and a pair of isolation switches. More particularly, each isolation switch of the pair can be coupled between one of the pair of bit lines and one of the pair of sense amplifier inputs wherein the isolation switches electrically couple the respective bit lines and the sense amplifier inputs responsive to a coupling signal provided on an isolation control signal line coupled to control electrodes of the isolation switches. In addition, an isolation control signal generator can be coupled to the isolation control signal line wherein the isolation control signal generator generates the coupling signal during operation of the sense amplifier for the memory cell array. Moreover, the isolation control signal generator can allow the isolation control signal line to float with respect to the isolation control signal generator during a first period of operation of the sense amplifier for the memory cell array.
Devices and methods according to embodiments of the present

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