Semiconductor memory device with testing function

Details Semiconductor memory device with testing function Semiconductor memory device with testing function

1996-09-19

1998-02-10

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Testing

36518905, G11C 2900

Patent

active

057176434

ABSTRACT:
Four I/O pads are allocated to a group from one end to the other. A test circuit is provided for each of the groups. The four I/O pads are only connected to a test data terminal of an IC tester while the rest of the I/O pads are not connected. The test circuit comprises: a test mode detection circuit for detecting the device shifting to the test mode; a test mode writing circuit for writing data inputted from one of the I/O pads into four memory cells; a coincidence circuit for determining whether the data read from the four memory cells coincide with each other; and a data output circuit for outputting the result to the I/O pad.

REFERENCES:
patent: 5228000 (1993-07-01), Yamagata
patent: 5400281 (1995-03-01), Morigami
patent: 5615166 (1997-03-01), Machida

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