Semiconductor memory device with test mode decision circuit

Details Semiconductor memory device with test mode decision circuit Semiconductor memory device with test mode decision circuit

2000-04-24

2001-07-31

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S222000

Reexamination Certificate

active

06269038

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices and particularly to an improvement of a test mode decision circuit in a dynamic random access memory (DRAM).
2. Description of the Background Art
DRAMs in general have more than one test mode. A DRAM enters a test mode when a test mode decision circuit provided in the DRAM detects the test mode. To prevent the DRAM from erroneously entering the test mode when an ordinary user is normally using the DRAM, the test mode decision circuit is configured to detect a super VIH level higher than a logical high level that is applied to an address pin in a WCBR (WE (a write enable signal), CAS (a column address strobe signal) and BEFORE RAS (a row address strobe signal)) cycle.
However, conventional DRAMs cannot enter more than one test mode simultaneously. In contrast, Japanese Patent Laying-Open No. 5-242698 discloses a DRAM capable of entering more than one test mode simultaneously. Once it has entered a test mode, however, the DRAM cannot enter another test mode. As such, the DRAM must first exit the test mode and thereafter enter two test modes simultaneously.
Furthermore, in a conventional DRAM a refresh operation is performed whenever the DRAM enters a test mode. As such, in the DRAM the refresh operation is performed when the DRAM already in a test mode also enters another test mode, so that the first test cannot be run accurately.
Furthermore, a DRAM can erroneously enter a test mode when the write enable signal, the column address strobe signal and the row address strobe signal are erroneously input in the WCBR cycle and the address pin also receives a high-voltage noise.
Japanese Patent Laying-Open No. 10-247399 discloses a DRAM which allows three different password signals to be input in three WCBR cycles and stored in a register and in the fourth WCBR cycle responds to an input address by entering a predetermined test mode. This DRAM, however, cannot enter more than one test mode simultaneously.
SUMMARY OF THE INVENTION
The present invention contemplates a semiconductor memory device prevented from erroneously entering a test mode.
In accordance with the present invention, a semiconductor memory device having a memory cell array includes a test mode decision circuit and a plurality of test control circuits. The test mode decision circuit activates a test mode entry signal in response to an address key when a write enable signal and a column address strobe signal are activated before a row address strobe signal is activated, and the test mode decision circuit selectively activates a plurality of test mode signals in response to an address key when with the test mode entry signal activated the write enable signal and the column address strobe signal are activated before the row address strobe signal is activated. The plurality of test control circuits are associated with a plurality of test mode signals. Each test control circuit responds to an associated test mode signal to run a predetermined test for the semiconductor memory device.
Preferably the test mode decision circuit activates one of the test mode signals and while continuously activating the test mode signal the test mode decision circuit also activates another test mode signal.
Preferably the semiconductor memory device also includes refresh means including refresh means refreshing the memory cell array when with the test mode entry signal inactivated the write enable signal and the column address strobe signal are activated before the row address strobe signal is activated.
Thus in accordance with the present invention it is not until the second WCBR cycle that the test mode decision circuit responds to an address key to activate a test mode. Thus the semiconductor memory device is less likely to erroneously enter a test mode.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5400290 (1995-03-01), Suma et al.
patent: 5999480 (1999-12-01), Ong et al.
patent: 5-242698 (1993-09-01), None
patent: 6-194424 (1994-07-01), None
patent: 10-247399 (1998-09-01), None

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