Semiconductor memory device with test mode and testing...

Details Semiconductor memory device with test mode and testing... Semiconductor memory device with test mode and testing...

2005-03-29

2005-03-29

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S230030, C365S233100, C365S239000

Reexamination Certificate

active

06873556

ABSTRACT:
A synchronous SRAM includes a register sequentially providing data signals of the burst length in a test mode, and a transfer circuit applying data signals output from the register to a memory array for burst-writing, and providing to an external source via an IO buffer a data signal read out in a burst manner later than the burst writing by 1 clock cycle. It is not necessary to additionally apply a data signal for writing. The required number of address signals can be reduced. Thus, testing can be simplified.

REFERENCES:
patent: 5483488 (1996-01-01), Sanada
patent: 20040151037 (2004-08-01), Benedix et al.
patent: 59-175100 (1984-10-01), None

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