Semiconductor memory device with test circuit

Details Semiconductor memory device with test circuit Semiconductor memory device with test circuit

2007-08-28

2007-08-28

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000

Reexamination Certificate

active

11194539

ABSTRACT:
A semiconductor memory device includes a memory cell array including a plurality of memory blocks, a plurality of redundancy sections respectively provided for the plurality of memory blocks and configured to be substituted for defective memory cells, a test circuit that carries out a test on the memory cell array and outputs defective data, first and second memory circuit that temporarily store the defective data, a first write circuit that writes the defective data alternately in the first and second memory circuits, a first read circuit that reads the defective data alternately from the first and second memory circuits, a plurality of third memory circuits respectively provided for the plurality of memory blocks, that store the defective data, and a second write circuit that writes defective data read by the first read circuit in a third memory circuit corresponding to a memory block in which an error occurred.

REFERENCES:
patent: 5295101 (1994-03-01), Stephens et al.
patent: 6714466 (2004-03-01), Park et al.
patent: 2004/0093539 (2004-05-01), Chadwick et al.
patent: 2004/0153925 (2004-08-01), Ronza et al.
patent: 2004/0225912 (2004-11-01), Ronza et al.
patent: 2000-260198 (2000-09-01), None
patent: 2002-184197 (2002-06-01), None

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