Semiconductor memory device with signal lines arranged...

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S063000

Reexamination Certificate

active

07149112

ABSTRACT:
A semiconductor memory device comprises a memory cell array including a plurality of data storage regions having a plurality of memory cells and a plurality of dummy regions occupying space between the plurality of data storage regions, at least one peripheral logic arranged around the memory cell array, and a control logic for controlling operations of the peripheral logic, wherein a plurality of signal lines for connecting the peripheral logic and the control logic are arranged in the plurality of dummy regions.

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patent: 5184321 (1993-02-01), Konishi et al.
patent: 6150728 (2000-11-01), Tsukude et al.
patent: 6320785 (2001-11-01), Yoshida et al.
patent: 6339541 (2002-01-01), Hardee et al.
patent: 6654283 (2003-11-01), Haddad
patent: 6762949 (2004-07-01), Fujisawa et al.
patent: 11-261036 (1999-09-01), None
patent: 2001-274366 (2001-05-01), None
patent: 2002-261174 (2002-09-01), None
patent: 10-2003-0032858 (2003-04-01), None
English Abstract Only *** Nonvolatile Semiconductor memory Mar. 10, 1998.
English Abstract Only *** Nonvolatile Semiconductor Memory Device and Producing method therefor Mar. 28, 2000.
English Abstract Only *** Manufacturing Method of Nonvolatile Semiconductor memory Mar. 02, 2001.
English Abstract Only *** Self Aligned Method of forming semicondoctor memory array of floating gate Oct. 16, 2002.

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