Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2007-10-23
2007-10-23
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S189120
Reexamination Certificate
active
11486002
ABSTRACT:
A semiconductor memory device with low power consumption in driving control signals of shift registers. The device contains a plurality of memory cell arrays each composed of a predetermined number of rows of memory cells. One set of shift registers are coupled to each cell array, and the nth set of shift registers successively activate word line selection signals according to a given control signal, so that the corresponding word lines of the nth cell array will be refreshed. Also coupled to each cell array is a shift register controller. The nth shift register controller provides a control signal to the nth set of shift registers when the nth cell array is being refreshed. When the refresh of that cell array is finished, the nth shift register controller forwards the control signal to the (n+1)th set of shift registers, thus initiating refresh operation for the (n+1)th cell array.
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Ito Shigemasa
Kawabata Kuninori
Mori Kaoru
Mori Katuhiro
Yamada Shin-ichi
Arent Fox LLP.
Le Vu A.
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