Semiconductor memory device with several access enabled using si

Details Semiconductor memory device with several access enabled using si Semiconductor memory device with several access enabled using si

1999-03-30

2000-10-17

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

Simultaneous operations

36518901, 36523006, 36523008, 36523001, 365233, G11C 700

Patent

active

061341541

ABSTRACT:
In a semiconductor memory device, a plurality of memory cells are arranged in a matrix. Each of the plurality of memory cells is connected to one of a plurality of word lines and is connected to one of a plurality of bit lines such that a plurality of columns are formed from the plurality of memory cells. A word line selecting section selects one of the plurality of word lines based on a first address. A first column selector selects one of the plurality of columns as a first column based on the first address. A second column selector selects another one of the plurality of columns as a second column based on a second address. An address data of a predetermined portion of the first address is not equal to an address data of the second address. An input/output section includes a first sense amplifier and a first buffer. A first read operation is performed to a first memory cell connected to the selected word line and the first column through the first sense amplifier and the first column selector and a first write operation is performed to a second memory cell connected to the selected word line and the second column through the first buffer and the second column selector.

REFERENCES:
patent: 5587950 (1996-12-01), Sawada et al.
patent: 5781480 (1998-07-01), Nogle et al.
patent: 5841730 (1998-11-01), Kai et al.
patent: 5892730 (1999-04-01), Sato et al.
patent: 5973955 (1999-10-01), Nogle et al.

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