Semiconductor memory device with sense circuit connected to...

Details Semiconductor memory device with sense circuit connected to... Semiconductor memory device with sense circuit connected to...

2011-08-16

2011-08-16

Le, Vu A (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S207000

Reexamination Certificate

active

08000130

ABSTRACT:
A semiconductor memory device comprises a word line; a bit line crossing the word line; a memory cell connected to intersection of the word line and the bit line; and a sense circuit connected to sense node coupled to the bit line. The sense circuit includes a first transistor of the first conduction type having a gate connected to the sense node, a second transistor of the second conduction type having a source connected to a first power supply, a drain connected to the sense node, and a gate connected to the drain of the first transistor, a third transistor having a source connected to the first power supply, a drain connected to the drain of the first transistor, and a gate connected to a control signal line, and a fourth transistor having a source connected to a second power supply, a drain connected to the source of the first transistor, and a gate connected to the control signal line. The sense circuit is activated with a control signal given to the control signal line.

REFERENCES:
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patent: 5850359 (1998-12-01), Liu
patent: 7724565 (2010-05-01), Barth et al.
patent: 2008/0084781 (2008-04-01), Piorkowski
John Wuu, et al., 'The Asynchronous 24MB On-Chip Level-3 Cache for a Dual-Core Itanium°-Family Processor, IEEE International Solid-State Circuits Conference, Session 26, 2005, pp. 488-489 and 618.

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