Semiconductor memory device with sense amplifier power...

Details Semiconductor memory device with sense amplifier power... Semiconductor memory device with sense amplifier power...

2000-09-26

2002-05-07

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Powering

C365S207000

Reexamination Certificate

active

06385115

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and particularly, to a power supply configuration for sense amplifier circuits sensing and amplifying a memory cell data.
2. Description of the Background Art
FIG. 23
is a diagram schematically showing a construction of a memory mat of a conventional semiconductor device. In
FIG. 23
, a memory array is divided into a plurality of memory blocks MB#
1
to MB#n each including a plurality of memory cells arranged in rows and columns. Sense amplifier bands SB#
1
to SB#n−1 each are arranged between memory blocks adjacent in a column direction and sense amplifier bands SB#
0
and SM#n are arranged outside the memory blocks MB#
1
and MB#n, respectively. In each sense amplifier band, sense amplifier circuits are arranged corresponding to columns of the adjacent memory blocks and the sense amplifier circuits are shred between the adjacent memory blocks. A memory array is divided into the plurality of memory blocks MB#
1
to MB#n and sense amplifier circuits are arranged on both sides of each of the memory blocks MB#
1
to MB#n to make shorter lengths of bit line pairs provided in correspondence to respective memory cell columns in each memory block and thereby loads thereon are reduced, so that a memory cell data at a sufficiently high voltage level is transmitted to a sense amplifier circuit at a high speed and a high-speed sense operation is realized.
In such a memory mat configuration, a power supply voltage and a ground voltage are supplied to the sense amplifier bands SB#
0
to SB#n in order that sense amplifiers sense and amplify memory cell data on corresponding columns. In a case where the power supply voltage and the ground voltage are transmitted over a long distance, levels of the power supply voltage and the ground voltage varies due to interconnection line resistance of power source voltage supply lines (including a power supply voltage line and a ground voltage line), whereby no correct sense operation can be performed. Further, with the presence of such interconnection line resistance, the power source voltage (power supply voltage and ground voltage) cannot be supplied to sense amplifiers at a high speed (variations of the power supply voltage cannot be suppressed). Therefore, the power supply line and the ground line are laid on the memory cell array in a meshed shape arrangement in order to supply the sense amplifier power supply voltage and the sense amplifier ground voltage in a stable manner to sense amplifier circuits included in the sense amplifier bands SB#
0
to SB#n.
FIG. 24
is a block diagram schematically showing a power supply configuration of a conventional semiconductor memory device. In
FIG. 24
, a main power supply line MPL is laid out so as to surround the memory mat. Subsidiary power supply lines SBPL are laid out so as to be connected to the main power supply line MPL and extends over the memory blocks MB#
1
to MB#n, and over the sense amplifier bands SB#
0
to SB#n. In each of the sense amplifier bands SB#
0
to SB#n, there is laid out a sense amplifier power supply line SAPL in order to transmit the power supply voltage to the sense amplifier circuits. To the main power supply line MPL, active sense amplifier power supply circuits ACVG
1
and ACVG
2
made active in an active cycle and generating a sense amplifier power supply voltage VCCA are connected and a standby sense amplifier power supply voltage circuit STVG maintaining a level of the power supply voltage VCCA on the main power supply line MPL is also connected. Here, an active cycle indicates an operating cycle in which rows (word lines) in a predetermined number of blocks among the memory blocks MB#
1
to MB#n are each driven to a selected state and the corresponding sense amplifier circuits operate. A standby cycle indicates an operating cycle in which all rows (word lines) in the memory blocks MB#
1
to MB#n are held in a non-selected state. In the standby cycle, the active sense amplifier power supply circuits ACVG
1
and ACVG
2
are held in an inactive state.
With the power supply line and the sense amplifier power supply lines SAPL transmitting the sense amplifier power supply voltage VCCA, laid on the memory mat in a meshed shape arrangement, interconnection line resistance of the sense amplifier power supply lines SAPL provided in the respective sense amplifier bands SB#
0
to SB#n are reduced equivalently and further a width of interconnection line is also larger equivalently, thereby enabling the power supply voltage VCCA to be supplied in a stable manner.
In
FIG. 24
, power supply lines transmitting the sense amplifier power supply voltage VCCA are shown and ground lines transmitting the ground voltage VSS are also laid on the memory mat in a meshed shape arrangement.
With the active sense amplifier power supply circuits ACVG
1
and ACVG
2
provided, currents are supplied onto the main power supply line MPL, the subsidiary power supply lines SBPL and the sense amplifier power supply lines SAPL from both sides of one end of the memory mat in a stable manner to prevent the power supply voltage of the sense amplifier power supply voltage VCCA from being distributed. Further, the active sense amplifier power supply circuits ACVG
1
and ACVG
2
are activated when the memory mat enters an active cycle and the sense amplifier circuits in a selected sense amplifier band operate to consume the sense amplifier power supply voltage VCCA, with the result that a level down in the sense amplifier power supply voltage VCCA is prevented from occurring. Therefore, the active sense amplifier power supply circuits ACVG
1
and ACVG
2
each are required to have at least a capability to compensate for a current consumed in the sense amplifier circuits and thus, have a comparatively large current drive capability.
On the other hand, while the standby sense amplifier power supply circuit STVG operates all time, requirement thereon is only to compensate for reduction in the sense amplifier power supply voltage VCCA caused by a leakage current in the standby cycle and a current drive capability of the standby sense amplifier power supply circuit STVG is small comparatively.
FIG. 25
is a circuit diagram showing a configuration of one sense amplifier circuit and its peripheral circuits included in a sense amplifier band. In
FIG. 25
, the sense amplifier band SB# is shared between the memory blocks MB#L and MB#R. The sense amplifier circuit includes a sense amplifier SA performing differential amplification of potentials on common bit lines CBL and ZCBL when activated and sense amplifier activation transistors P
1
and N
1
which become conductive when a sense amplifier activation signal ZSOP and SOP are activated, to transmit the sense amplifier power supply voltage VCCA on the sense amplifier power supply line and the sense amplifier ground voltage VSS on the sense amplifier ground line to the sense amplifier SA. A pair of the sense amplifier activation transistors P
1
and N
1
are provided commonly to a predetermined number of sense amplifiers. A sense amplifier SA includes P channel MOS transistors P
2
and P
3
cross-coupled to each other and N channel MOS transistors N
2
and N
3
cross-coupled to each other.
The sense amplifier SA are connected to bit lines BLL and ZBLL of the memory block MB#L through a bit line isolation gate BIGL and bit lines BLR and ZBLR of the memory block MB#R through a bit line isolation gate BIGR. In the memory block MB#L, a memory cell MC is placed corresponding to an intersection of the word line WLL and the bit line BLL or ZBLL and likewise, in the memory block MB#R, a memory cell MC is placed corresponding to an intersection of the word line WLR and the bit line BLR or ZBLR. In
FIG. 25
, memory cells MC are placed at the intersections between the word line WLL and the bit line ZBLL and between the word

Affiliated with

Also associated with

Rating

Semiconductor memory device with sense amplifier power... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device with sense amplifier power..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device with sense amplifier power... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2914530