Delay locked loop of a DDR SDRAM

Details Delay locked loop of a DDR SDRAM Delay locked loop of a DDR SDRAM

2001-05-30

2002-05-28

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000

Reexamination Certificate

active

06396322

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device, and, more particularly, to a delay locked loop of a semiconductor memory device.
BACKGROUND OF THE INVENTION
Major characteristics of a semiconductor memory are high speed, low power consumption and high integration. Recently, there has been a tendency to focus on high speed memory such as DDR (Double Data Rate) synchronous memory and RAMBUS DRAM from EDO (Extended Data Output) memory and synchronous memory. Recently, access times around 100 MHz have been accomplished by using a post charge logic and access times higher than that speed have been enabled by eliminating clock skew with a PLL (Phase Locked Loop) or a DLL (Delay Locked Loop). However, at a clock frequency higher than 200 MHz, an additional clock storage node, a bus line or a control logic is required, which results in enlarged chip size.
Efforts to realize a high speed semiconductor memory have resulted in the development of fast page EDO memory, synchronous memory, DDR synchronous memory and RAMBUS memory These memories are different from each other in speed, but all have inevitable limits.
Among the memories described above, the synchronous memory outputs data at a rising edge of a clock and inputs data at next rising edge of the clock. The period from the output strobe of data to the time at which data is outputted is tAC (Clock Access Time).
In 250 MHz operation, tAC is equal to tCK (Clock Cycle Time), which causes the DRAM controller to miss inputting data at the next clock pulse. That is, data cannot be read and written properly at speeds over 250 MHz.
FIG. 1
is a timing diagram of the tAC (Clock Access Time) and the clock skew. Referring to
FIG. 1
, the tAC consists of the clock skew and the data buffering time. The clock skew means the delay of an internal clock relative to an external clock. This delay is due to clock drivers. When the delay of an input buffer to which the external clock is applied is d
1
` and the delay of clock drivers serially coupled to the input buffer is d
2
, the clock skew is d
1
+d
2
. The phase locked loop (PLL) or delay locked loop is used to reduce that clock skew so as to realize a higher speed memory.
However, the phase locked loop or delay locked loop requires a number of cycles to lock which takes a length of time tLOCK (Locking time) and subsequently increases standby current.
FIGS. 2A-2B
respectively provide a block diagram and a timing diagram of a PLL. Referring to
FIG. 2A
, the phase locked loop includes an input buffer
200
for buffering an external clock, a phase error detector
210
for detecting a phase difference between the external clock from the input buffer
200
and a fed-back clock signal from a delay monitoring circuit
240
, a low pass filter
220
for eliminating high frequency components of the output of the phase error detector
210
, a voltage controlled oscillator
230
for generating a clock signal which is proportional to the output of the low pass filter
220
, the delay monitoring circuit
240
coupled to the output of the voltage controlled oscillator
230
for checking that the phase locked loop is locked normally, and a clock driver
250
for driving the output of the voltage controlled oscillator
230
as a clock output signal clkPLL.
To eliminate the clock skew by comparing the phase of the external clock with that of the internal clock, i.e., to have no phase error, hundreds of cycles are repeated for the tLOCK. Furthermore, in CMOS processing, it is difficult to design the voltage controlled oscillator
230
or the low pass filter
220
. Parameters of the voltage controlled oscillator
230
and the low pass filter
220
have no operational voltage variation and no processing margin because of lower gain and noise requirements. To solve this problem, a synchronous delay line is introduced. Here, a synchronous mirror delay will be described. The synchronous mirror delay cannot be used for DDR synchronous memory because it operates by detecting the rising edge of the clock only.
FIGS. 3A and 3B
respectively illustrate a block diagram and a timing diagram of a synchronous mirror delay. Referring to
FIG. 3A
, the synchronous mirror delay includes an input buffer
300
for buffering an external clock signal from an external clock, a delay monitoring circuit (DMC)
310
for delaying in time the output of the input buffer
300
by a skew to be compensated, a forward delay array (FDA)
320
for adjusting the time delay of output of the delay monitoring circuit
310
in a first direction, a mirror control circuit (MCC)
330
coupled to the outputs of the forward delay array
320
and the input buffer
300
for developing a clock signal adjusted by the adjusted time delay, a backward delay array (BDA)
340
for adjusting the time delay of the output of the mirror control circuit
330
in a second direction, an output circuit
350
coupled to the output of the backward delay array
340
for outputting a delay locked loop clock signal (CLKsmd).
An internal clock can be synchronized with the external clock in 2 clocks, but a unit delay restricts a jitter. The length of a delay chain should be increased to reduce this, which leads to increased area. As compared to the number of clocks required by the DLL that is implemented by a feed-back circuit, the synchronous mirror delay (SMD) reduces the clock skew by two sequential pulses tLOCK. The forward delay array
320
has an input and a number of outputs. The backward delay array
340
has a number of inputs and an output. Each of the forward delay array
320
and the backward delay array
340
has a delay unit, tDF (Forward Delay) and tDB (Backward Delay), respectively. The delay units are disposed in parallel and operated in opposite directions from each other. This is for simplicity and compactness of the circuit. The output of the forward delay array is coupled to the input of the backward delay array through the mirror control circuit
330
.
FIG. 4
is a more detailed circuit diagram of a synchronous mirror delay. Referring to
FIG. 4
, the synchronous mirror delay includes an input buffer
300
for buffering an external clock, a delay circuit
310
for delaying in time the output of the input buffer
300
, a forward delay array
320
receiving the time delayed clock pulse from the delay circuit
310
, a mirror control circuit
330
receiving the outputs of the forward delay array
320
and the delay circuit
310
, a backward delay array
340
receiving the outputs of the mirror control circuit
330
, and an output circuit
350
for receiving the output of the backward delay array
340
to generate the output signal (Int.CLK).
In particular, a first stage of the forward delay array
320
includes a NAND gate
321
receiving the output of the delay circuit
310
and a power voltage. It also includes an inverter
322
receiving the output of the NAND gate
321
. A second stage includes (a) a NAND gate
323
which receives the output of the inverter
322
and the power voltage, and (b) an inverter
324
which receives the output of the NAND gate
323
. A third stage includes a NAND gate
325
which receives the output of the inverter
324
and an output of the mirror control circuit
330
. It also includes an inverter
326
which receives the output of the NAND gate
325
. A number of other stages coupled serially with and constructed similarly to the third stage are also included.
The mirror control circuit
330
includes a number of NAND gates. The output of the inverter of each stage of the forward delay array
320
and the output of the delay circuit
310
is coupled to a respective one of each of the NAND gates.
The backward delay array
340
includes a series of stages comprising a NAND gate and an inverter. An output of a stage of the mirror control circuit
330
and the output of the inverter of the previous stage of the mirror control circuit
330
is input to the NAND gates as shown in FIG.
4
.
The output circuit
350
includes an even number of inverters receiving the output of the final stage o

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