Semiconductor memory device with row redundancy

Details Semiconductor memory device with row redundancy Semiconductor memory device with row redundancy

1997-04-17

1999-03-30

Nelms, David

Static information storage and retrieval

Read/write circuit

Bad bit

36518522, 36518901, 3652335, G11C 700

Patent

active

058897100

ABSTRACT:
A semiconductor memory device includes: a matrix of memory cells including a plurality of rows of memory cells; first means for generating a first internal timing signal activated upon changing of a current address supplied to the memory device, the first timing signal remaining activated for a prescribed time substantially at the beginning of a read cycle of the memory device; row address decoding means supplied by the current address for selecting a row of memory cells; second means for storing defective addresses of defective rows in the matrix of memory cells, for comparing the defective addresses with a current address supplied to the memory device, for selecting a redundancy row when the current address coincides with one of the defective addresses and for correspondingly deactivating the row address decoding means to prevent the selection of the defective row. The memory device includes redundancy control means supplied by the first timing signal, the redundancy control means enabling said row address decoder means at the beginning of the read cycle independently of the current address and maintains the row address decoder means enabled until the first timing signal is deactivated.

REFERENCES:
patent: 4811298 (1989-03-01), Helwig et al.
patent: 4849938 (1989-07-01), Furutani et al.
patent: 4858192 (1989-08-01), Tatsumi et al.

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