Semiconductor memory device with restricted potential amplitude

Details Semiconductor memory device with restricted potential amplitude Semiconductor memory device with restricted potential amplitude

1992-07-21

1994-02-08

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

For complementary information

365203, 365207, 365208, G11C 700

Patent

active

052854167

ABSTRACT:
In a DRAM having two I/O lines commonly provided for reading and writing data and an amplifying circuit for providing a read data signal by amplifying potential difference between the two I/O lines, a potential difference control circuit 8 is provided which includes detecting circuits each having a parallel connected circuit of two MOS transistors each being diode-connected, and a switch circuit which is rendered conductive only at data reading.
Since the maximum value of the potential difference between the two I/O lines during data reading is controlled to several times that of the threshold voltage of a MOS transistor, the time necessary for equalizing the I/O lines at data reading can be reduced. Consequently, the speed of change of the output potential of the amplifying circuit changing to the potential corresponding to the data stored in the memory cell MC is increased, and therefore the access time is reduced.

REFERENCES:
patent: 5115412 (1992-05-01), Tobita
patent: 5124947 (1992-06-01), Nakada
Session XVI: Static RAMs THPM 1.62: A 30ns 256K Full CMOS SRAM, Okazaki et al., 1986 IEEE International Solid-State Circuits Conference, pp. 204-205.

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