Semiconductor memory device with replacement programming...

Details Semiconductor memory device with replacement programming... Semiconductor memory device with replacement programming...

2000-11-06

2002-01-15

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S225700, C365S201000, C365S189070

Reexamination Certificate

active

06339554

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device having a spare memory cell.
2. Description of the Background Art
The arrangement of a main portion of a conventional semiconductor memory device will be described in relation to FIG.
10
. In the diagram, memory cells are represented by reference characters m
0
to m
63
, word lines disposed corresponding to the rows are represented by reference characters w
0
to w
63
, and a bit line disposed corresponding to a column is represented by reference characters “bit,” respectively. Further, a spare memory cell that can replace a memory cell is represented by reference characters r
0
, and a spare word line that can replace a word line is represented by reference characters sw
0
.
Bit line “bit” is connected to memory cells m
0
to m
63
and spare memory cell r
0
, and transmits data read from or to be written into memory cells m
0
to m
63
and spare memory cell r
0
. Word lines w
0
to w
63
are connected to memory cells m
0
to m
63
, and each word line sends a selecting signal to a corresponding memory cell. Spare word line sw
0
is connected to spare memory cell r
0
and sends a selecting signal to the corresponding spare memory cell.
As shown in
FIG. 10
, the conventional semiconductor memory device includes a replacement control circuit
100
#
0
, a decoder
105
#
0
including programming circuits
102
#
0
to
102
#
5
and logic circuits
103
#
0
to
103
#
63
, a comparator
120
#
0
, and an AND circuit
119
#
0
. Each of replacement control circuit
100
#
0
and programming circuits
102
#
0
to
102
#
5
includes a fuse.
When a defective memory cell is replaced with a spare memory cell (using spare word line sw
0
), the fuse included in replacement control circuit
100
#
0
is blown. Thus, a replacement control signal R
0
of a logic high or H level indicating the use of the spare memory cell will be output.
The fuse included in each of programming circuits
102
#
0
to
102
#
5
is blown according to an address of the defective memory cell. The output from the programming circuit having a blown fuse attains the H level. Signals g
0
to g
5
are output from programming circuits
102
#
0
to
102
#
5
.
Comparator
120
#
0
compares a 6-bit address signal ad<0:5> with signals g
0
to g
5
, and outputs an H level signal when a match occurs. AND circuit
119
#
0
activates spare word line sw
0
according to replacement control signal R
0
and a comparison result from comparator
120
#
0
.
Logic circuits
103
#
0
to
103
#
63
each include AND circuits
104
A and
104
B and an NAND circuit
106
. Logic circuits
103
#
0
to
103
#
63
are provided corresponding to a 64-bit address. Each of logic circuits
103
#
0
to
103
#
63
receives a signal g
0
or an inverted signal /g
0
of signal g
0
, a signal g
1
or an inverted signal /g
1
of signal g
1
, a signal g
2
or an inverted signal /g
2
of signal g
2
, a signal g
3
or an inverted signal /g
3
of signal g
3
, a signal g
4
or an inverted signal /g
4
of signal g
4
, and a signal g
5
or an inverted signal /g
5
of signal g
5
.
In the diagram, logic circuit
103
#
0
receives signals g
0
, g
1
, g
2
, g
3
, g
4
, and g
5
, while logic circuit
103
#
63
receives signals /g
0
, /g
1
, /g
2
, /g
3
, /g
4
, and /g
5
. NAND circuit
106
receives replacement control signal R
0
and outputs from AND circuits
104
A and
104
B. Row address non-selection signal t
0
to t
63
are output from logic circuits
103
#
0
to
103
#
63
, respectively.
The conventional semiconductor memory device further includes AND circuits
108
#
0
to
108
#
63
. AND circuits
108
#
0
to
108
#
63
are respectively provided to word lines w
0
to w
63
. AND circuits
108
#
0
to
108
#
63
receive row address nonselection signals t
0
to t
63
and decode signals a
0
to a
63
, respectively. Decode signals a
0
to a
63
are obtained by decoding address signal ad<0:5> by a row decoder not shown. Word lines w
0
to w
63
are respectively activated according to outputs from AND circuits
108
#
0
to
108
#
63
.
When the memory cells are all normal, replacement control signal R
0
is at a logic low or L level so that spare word line sw
0
is in the inactive state. In this case, row address non-selection signals t
0
to t
63
attain the H level. One of word lines w
0
to w
63
is activated according to decode signals a
0
to a
63
.
When a defect is found in a memory cell and the defective memory cell is to be replaced with a spare memory cell, a fuse in replacement control circuit
100
#
0
and a corresponding fuse in programming circuits
102
#
0
to
102
#
5
are blown.
An example is given in which a memory cell m
0
is defective. Assume that the address of word line w
0
is “000000” (=ad<0:5>). In this case, all the fuses in programming circuits
102
#
0
to
102
#
5
are blown. Signals g
0
to g
5
all attain the H level so that signal t
0
output from logic circuit
103
#
0
attains the L level. Consequently, when an address signal designating memory cell m
0
is input and decode signal a
0
attains the H level, word line w
0
is not activated.
At this time, comparator
120
#
0
outputs an H level signal since the input address signal ad<0:5> corresponds to signals g
0
to g
5
. As a result, spare word line sw
0
is activated.
FIG. 11
shows another arrangement of the main portion of a conventional semiconductor memory device. The conventional semiconductor memory device shown in
FIG. 11
has an arrangement for replacing two word lines. In the diagram, spare memory cells that can replace the memory cells are represented by reference characters r
0
and r
1
, and spare word lines that can replace word lines are represented by reference characters sw
0
and sw
1
.
A bit line “bit” is connected to memory cells m
0
to m
63
and spare memory cells r
0
and r
1
, and transmits data read from or to be written into memory cells m
0
to m
63
and spare memory cells r
0
and r
1
. Spare word lines sw
0
and sw
1
are connected to spare memory cells r
0
and r
1
, and each spare word line sends a selecting signal to a corresponding spare memory cell.
As shown in
FIG. 11
, the conventional semiconductor memory device includes replacement control circuits
100
#
0
and
100
#
1
, decoders
105
#
0
and
105
#
1
, comparators
120
#
0
and
120
#
1
, and AND circuits
119
#
0
and
119
#
1
.
Replacement control circuit
100
#
1
has the same arrangement as replacement control circuit
100
#
0
, and its fuse is blown when spare word line sw
1
is to be used. Consequently, an H level replacement control signal R
1
is output.
The arrangement of decoder
105
#
1
is the same as that of decoder
105
#
0
. The fuse included in each of programming circuits
102
#
0
to
102
#
5
is blown according to an address of a defective memory cell. Hereinafter, the outputs from programming circuits
102
#
0
to
102
#
5
included in decoder
105
#
1
will be referred to as signals h
0
to h
5
.
Each of logic circuits
103
#
0
to
103
#
63
included in decoder
105
#
1
receives a signal h
0
or an inverted signal /h
0
of signal h
0
, a signal h
1
or an inverted signal /h
1
of signal h
1
, a signal h
2
or an inverted signal /h
2
of signal h
2
, a signal h
3
or an inverted signal /h
3
of signal h
3
, a signal h
4
or an inverted signal /h
4
of signal h
4
, and a signal h
5
or an inverted signal /h
5
of signal h
5
. Logic circuits
103
#
0
to
103
#
63
perform logical processing according to replacement control signal R
1
. Row address non-selection signals output from decoder
105
#
1
will be referred to as signals u
0
to u
63
.
Comparator
120
#
1
has the same arrangement as comparator
120
#
0
, compares address signal ad<0:5> with sign

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